MARINA

Microarchitecture and Integrated Circuits Research Group

Publications

2014

  • L. Zhao and J. Draper, “Consolidated Conflict Detection for Hardware Transactional Memory,” in Parallel Architecture and Compilation Techniques, 2014 23rd International Conference on, 2014.
    [Bibtex]
    @INPROCEEDINGS{C2DPACT, 
    author={Zhao, Lihang and Draper, Jeffrey}, 
    booktitle={Parallel Architecture and Compilation Techniques, 2014 23rd International Conference on}, 
    title={Consolidated Conflict Detection for Hardware Transactional Memory}, 
    year={2014}, 
    month={August}, 
    }
  • G. Neela and J. Draper, “A multi-mode energy-efficient double-precision floating-point multiplier,” in Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on, 2014, pp. 29-32.
    [Bibtex]
    @inproceedings{neela2014multi,
      title={A multi-mode energy-efficient double-precision floating-point multiplier},
      author={Neela, Gopi and Draper, Jeffrey},
      booktitle={Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on},
      pages={29--32},
      year={2014},
      organization={IEEE},}
  • G. Neela and J. Draper, “Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach,” in VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on, 2014, pp. 154-159.
    [Bibtex]
    @inproceedings{neela2014modeling,
      title={Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach},
      author={Neela, Gopi and Draper, Jeffrey},
      booktitle={VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on},
      pages={154--159},
      year={2014},
      organization={IEEE},}
  • G. Neela and J. Draper, “Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC,” in Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, 2014, pp. 802-805.
    [Bibtex]
    @inproceedings{neela2014optimal,
      title={Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC},
      author={Neela, Gopi and Draper, Jeffrey},
      booktitle={Circuits and Systems (ISCAS), 2014 IEEE International Symposium on},
      pages={802--805},
      year={2014},
      organization={IEEE},}
  • [DOI] L. Zhao, L. Chen, and J. Draper, “Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory,” in Parallel and Distributed Processing Symposium, 2014 IEEE 28th International, 2014, pp. 605-614.
    [Bibtex]
    @INPROCEEDINGS{6877293, 
    author={Zhao, Lihang and Chen, Lizhong and Draper, Jeffrey}, 
    booktitle={Parallel and Distributed Processing Symposium, 2014 IEEE 28th International}, 
    title={Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory}, 
    year={2014}, 
    month={May}, 
    pages={605-614}, 
    keywords={Chip Multiprocessor;HTM;PUNO;Transactional Memory}, 
    doi={10.1109/IPDPS.2014.69}, 
    ISSN={1530-2075},}
  • F. Kashfi and J. Draper, “Thermal sensor allocation for 3DICs using three dimensional thermal sensors,” Microelectronics Journal, vol. 45, iss. 5, pp. 500-507, 2014.
    [Bibtex]
    @article{kashfi2014thermal,
      title={Thermal sensor allocation for 3DICs using three dimensional thermal sensors},
      author={Kashfi, Fatemeh and Draper, Jeff},
      journal={Microelectronics Journal},
      volume={45},
      number={5},
      pages={500--507},
      year={2014},
      publisher={Elsevier},}

2013

  • A. Deshpande and J. Draper, “Leakage Energy Estimates for HPC Applications,” in Proceedings of the 1st International Workshop on Energy Efficient Supercomputing, 2013.
    [Bibtex]
    @inproceedings{Deshpande:2013:LEE:2536430.2536431,
     author = {Deshpande, Aditya and Draper, Jeffrey},
     title = {Leakage Energy Estimates for HPC Applications},
     booktitle = {Proceedings of the 1st International Workshop on Energy Efficient Supercomputing},
     series = {E2SC '13},
     year = {2013},
    }
  • A. Deshpande and J. Draper, “Quantifying the Dominance of Leakage Energy in Large-Scale System Caches,” in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2013.
    [Bibtex]
    @inproceedings{Aditya:2013:SC,
     author = {Deshpande, Aditya and Draper, Jeffrey},
     title = {Quantifying the Dominance of Leakage Energy in Large-Scale System Caches},
     booktitle = {Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis},
     series = {SC '13},
     year = {2013},
    }
  • L. Zhao, L. Chen, and J. Draper, “PUNO: Predictive Unicast and Notification to Mitigate the Mismatch between Coherence Protocol and Conflict Detection in HTM,” in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2013.
    [Bibtex]
    @inproceedings{Lihang:2013:SC,
     author = {Zhao, Lihang and Chen, Lizhong and Draper, Jeffrey},
     title = {PUNO: Predictive Unicast and Notification to Mitigate the Mismatch between Coherence Protocol and Conflict Detection in HTM},
     booktitle = {Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis},
     series = {SC '13},
     year = {2013},
    }
  • [DOI] W. Choi and J. Draper, “Improving Utilization of Hardware Signatures in Transactional Memory,” Parallel and Distributed Systems, IEEE Transactions on, vol. 24, iss. 11, pp. 2230-2239, 2013.
    [Bibtex]
    @ARTICLE{6327189, 
    author={Woojin Choi and Draper, J.}, 
    journal={Parallel and Distributed Systems, IEEE Transactions on}, 
    title={Improving Utilization of Hardware Signatures in Transactional Memory}, 
    year={2013}, 
    volume={24}, 
    number={11}, 
    pages={2230-2239}, 
    keywords={digital signatures;parallel programming;transaction processing;hardware signatures;parallel programs;programmer productivity;read- and write-signatures;transactional memory;Benchmark testing;Hardware;Indexes;Instruction sets;Merging;Monitoring;Bloom filters;Hardware transactional memory;conflict detection;signatures;unified signatures}, 
    doi={10.1109/TPDS.2012.292}, 
    ISSN={1045-9219},}
  • G. Neela and J. Draper, “Techniques for Assigning Inter-Tier Signals to Bondpoints in a Face-to-Face Bonded 3DIC,” in Proceedings of the IEEE International 3D Systems Integration Conference, 2013.
    [Bibtex]
    @inproceedings{Neela:2013:AAE:2483028.2483107,
     author = {Neela, Gopi and Draper, Jeffrey},
     title = {Techniques for Assigning Inter-Tier Signals to Bondpoints in a Face-to-Face Bonded 3DIC},
     booktitle = {Proceedings of the IEEE International 3D Systems Integration Conference},
     series = {3DIC '13},
     year = {2013},
    }
  • [DOI] G. Neela and J. Draper, “An asymmetric adaptive-precision energy-efficient 3DIC multiplier,” in Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, 2013, pp. 269-274.
    [Bibtex]
    @inproceedings{Neela:2013:AAE:2483028.2483107,
     author = {Neela, Gopi and Draper, Jeffrey},
     title = {An asymmetric adaptive-precision energy-efficient 3DIC multiplier},
     booktitle = {Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI},
     series = {GLSVLSI '13},
     year = {2013},
     isbn = {978-1-4503-2032-0},
     location = {Paris, France},
     pages = {269--274},
     numpages = {6},
     url = {http://doi.acm.org/10.1145/2483028.2483107},
     doi = {10.1145/2483028.2483107},
     acmid = {2483107},
     publisher = {ACM},
     keywords = {3 dimensional integrated circuits, 3dic, asymmetric variable precision, chip stacking, energy efficient, multiplier, precision, variable precision},
    }
  • [DOI] F. Kashfi and J. Draper, “Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs,” in Digital System Design (DSD), 2013 Euromicro Conference on, 2013, pp. 404-411.
    [Bibtex]
    @INPROCEEDINGS{6628306,
    author={Kashfi, Fatemeh and Draper, Jeff},
    booktitle={Digital System Design (DSD), 2013 Euromicro Conference on},
    title={Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs},
    year={2013},
    pages={404-411},
    keywords={Equations;Linear programming;Optimization;Reliability;Stacking;Thermal analysis;Wires},
    doi={10.1109/DSD.2013.51},}
  • [DOI] L. Zhao and J. Draper, “Implementation of hybrid version management in hardware transactional memory,” in Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, 2013, pp. 777-780.
    [Bibtex]
    @INPROCEEDINGS{6571962,
    author={Lihang Zhao and Draper, J.},
    booktitle={Circuits and Systems (ISCAS), 2013 IEEE International Symposium on},
    title={Implementation of hybrid version management in hardware transactional memory},
    year={2013},
    pages={777-780},
    keywords={integrated memory circuits;logic design;microprocessor chips;parallel programming;Sun Rock processor design;hardware transactional memory;hybrid version management;parallel programming;Buffer storage;Hardware;Hybrid power systems;Memory management;Program processors;Random access memory;Registers},
    doi={10.1109/ISCAS.2013.6571962},
    ISSN={0271-4302},}
  • [DOI] G. Neela and J. Draper, “Logic-on-logic partitioning techniques for 3-dimensional integrated circuits,” in Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, 2013, pp. 789-792.
    [Bibtex]
    @INPROCEEDINGS{6571965,
    author={Neela, G. and Draper, J.},
    booktitle={Circuits and Systems (ISCAS), 2013 IEEE International Symposium on},
    title={Logic-on-logic partitioning techniques for 3-dimensional integrated circuits},
    year={2013},
    pages={789-792},
    keywords={integrated circuit design;logic partitioning;three-dimensional integrated circuits;3DIC design flow;chip footprint;design for 3D approach;design partitioning technique;integration platform;interconnect delay;logic-on-logic partitioning technique;logic-on-logic stacked 3DIC;search space;three dimensional integrated circuits;transistor scaling;Delays;Design automation;Integrated circuits;Optimization;Security;Stacking},
    doi={10.1109/ISCAS.2013.6571965},
    ISSN={0271-4302},}
  • [DOI] L. Zhao, W. Choi, L. Chen, and J. Draper, “In-network traffic regulation for Transactional Memory,” in Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, pp. 520-531.
    [Bibtex]
    @inproceedings{Zhao:2013:ITR:2495252.2495483,
     author = {Zhao, Lihang and Choi, Woojin and Chen, Lizhong and Draper, Jeffrey},
     title = {In-network traffic regulation for Transactional Memory},
     booktitle = {Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)},
     series = {HPCA '13},
     year = {2013},
     isbn = {978-1-4673-5585-8},
     pages = {520--531},
     numpages = {12},
     url = {http://dx.doi.org/10.1109/HPCA.2013.6522346},
     doi = {10.1109/HPCA.2013.6522346},
     acmid = {2495483},
     publisher = {IEEE Computer Society},
    }

2012

  • [DOI] W. Choi, L. Zhao, and J. Draper, “Mileage-based contention management in transactional memory,” in Proceedings of the 21st international conference on Parallel architectures and compilation techniques, 2012, pp. 471-472.
    [Bibtex]
    @inproceedings{Choi:2012:MCM:2370816.2370902,
     author = {Choi, Woojin and Zhao, Lihang and Draper, Jeff},
     title = {Mileage-based contention management in transactional memory},
     booktitle = {Proceedings of the 21st international conference on Parallel architectures and compilation techniques},
     series = {PACT '12},
     year = {2012},
     isbn = {978-1-4503-1182-3},
     location = {Minneapolis, Minnesota, USA},
     pages = {471--472},
     numpages = {2},
     url = {http://doi.acm.org/10.1145/2370816.2370902},
     doi = {10.1145/2370816.2370902},
     acmid = {2370902},
     publisher = {ACM},
     keywords = {contention management, mileage, transactional memory},
    }
  • [DOI] A. Deshpande and J. Draper, “Comparing squaring and cubing units with multipliers,” in Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on, 2012, pp. 466-469.
    [Bibtex]
    @INPROCEEDINGS{6292058,
    author={Deshpande, A. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on}, title={Comparing squaring and cubing units with multipliers},
    year={2012},
    month={aug.},
    volume={},
    number={},
    pages={466 -469},
    keywords={Algorithm design and analysis;Approximation algorithms;Clocks;Computers;Hardware;Software;Very large scale integration;VLSI;logic design;multiplying circuits;VLSI system;complex functional unit;dedicated cubing unit;dedicated squaring unit;general purpose multiplier design;hardware accelerator;latency penalty;power consumption;power penalty;power requirement;},
    doi={10.1109/MWSCAS.2012.6292058},
    ISSN={1548-3746},}
  • F. Kashfi and J. Draper, “Thermal sensor distribution method for 3D Integrated Circuits using efficient thermal map modeling,” in Thermal Investigations of ICs and Systems (THERMINIC), 2012 18th International Workshop on, 2012, pp. 1-6.
    [Bibtex]
    @INPROCEEDINGS{6400628,
    author={Kashfi, Fatemeh and Draper, Jeff},
    booktitle={Thermal Investigations of ICs and Systems (THERMINIC), 2012 18th International Workshop on}, title={Thermal sensor distribution method for 3D Integrated Circuits using efficient thermal map modeling},
    year={2012},
    month={sept.},
    volume={},
    number={},
    pages={1 -6},
    keywords={},
    doi={},
    ISSN={},}
  • [DOI] F. Kashfi and J. Draper, “Thermal sensor design for 3D ICs,” in Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on, 2012, pp. 482-485.
    [Bibtex]
    @INPROCEEDINGS{6292062,
    author={Kashfi, F. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on}, title={Thermal sensor design for 3D ICs},
    year={2012},
    month={aug.},
    volume={},
    number={},
    pages={482 -485},
    keywords={Correlation;Heat transfer;Heating;Ring oscillators;Temperature measurement;Temperature sensors;integrated circuit packaging;thermal management (packaging);thermal stresses;three-dimensional integrated circuits;3D IC technology;TSV;high power density;ring oscillator;temperature stress;thermal correlation;thermal exchanger;thermal management;thermal measurement;thermal sensor design;three dimensional integrated circuit;through silicon vias;volumetric spatial hotspot;},
    doi={10.1109/MWSCAS.2012.6292062},
    ISSN={1548-3746},}
  • [DOI] G. Neela and J. Draper, “Challenges in 3DIC implementation of a design using current CAD tools,” in Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on, 2012, pp. 478-481.
    [Bibtex]
    @INPROCEEDINGS{6292061,
    author={Neela, G. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on}, title={Challenges in 3DIC implementation of a design using current CAD tools},
    year={2012},
    month={aug.},
    volume={},
    number={},
    pages={478 -481},
    keywords={Bonding;Clocks;Delay;Design automation;Stacking;Standards;circuit CAD;three-dimensional integrated circuits;2D design;3D chip stacking technology;3DIC;MOSIS organization;Tezzaron-Global Foundries;academia;bonded tiers;chip footprint;current CAD tools;industry standard CAD tools;partition criterion;precision floating point unit;process technology package;},
    doi={10.1109/MWSCAS.2012.6292061},
    ISSN={1548-3746},}
  • [DOI] L. Zhao, W. Choi, and J. Draper, “SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory,” in Parallel Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International, 2012, pp. 95-106.
    [Bibtex]
    @INPROCEEDINGS{6267827,
    author={Lihang Zhao and Woojin Choi and Draper, J.},
    booktitle={Parallel Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International}, title={SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory},
    year={2012},
    month={may},
    volume={},
    number={},
    pages={95 -106},
    keywords={Buffer storage;Concurrent computing;Hardware;Instruction sets;Memory management;Pathology;Runtime;cache storage;concurrency control;configuration management;transaction processing;HTM system;SEL-TM;STAMP benchmark;complex cache protocol;concurrency;conflict detection;eager system;eagerly-managed memory addresses;hardware transactional memory;hybrid management;intelligent hardware scheme;lazily-managed memory addresses;lazy system;lazy version management;memory block;performance degradation;selective eager-lazy management;selective-eager-lazy HTM;transaction write set;Conflict Point Discovery;Hardware Transactional Memory;SEL-TM;Version Management;},
    doi={10.1109/IPDPS.2012.19},
    ISSN={1530-2075},}
  • [DOI] L. Zhao and J. Draper, “On the Correctness of Mixing Lazy and Eager Version Management in Transactions,” in Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012 IEEE 26th International, 2012, pp. 2534-2537.
    [Bibtex]
    @INPROCEEDINGS{6270887,
    author={Lihang Zhao and Draper, J.},
    booktitle={Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012 IEEE 26th International}, title={On the Correctness of Mixing Lazy and Eager Version Management in Transactions},
    year={2012},
    month={may},
    volume={},
    number={},
    pages={2534 -2537},
    keywords={Buffer storage;Coherence;Concurrent computing;Hardware;Instruction sets;Memory management;concurrency control;configuration management;parallel programming;storage management;transaction processing;HTM approach;HTM systems;atomicity requirement;conflict detection;conflict serializability requirement;eager system;eager version management;execution behavior;hardware transactional memory;lazy system;lazy version management;memory coherence formal model;optimistic concurrency-control construct;parallel programming;parallel workload;transaction execution correctness;},
    doi={10.1109/IPDPSW.2012.320},
    ISSN={},}
  • [DOI] L. Zhao, W. Choi, and J. Draper, “TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency,” in Proceedings of the 21st international conference on Parallel architectures and compilation techniques, 2012, pp. 439-440.
    [Bibtex]
    @inproceedings{Zhao:2012:TCH:2370816.2370885,
     author = {Zhao, Lihang and Choi, Woojin and Draper, Jeffrey},
     title = {TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency},
     booktitle = {Proceedings of the 21st international conference on Parallel architectures and compilation techniques},
     series = {PACT '12},
     year = {2012},
     isbn = {978-1-4503-1182-3},
     location = {Minneapolis, Minnesota, USA},
     pages = {439--440},
     numpages = {2},
     url = {http://doi.acm.org/10.1145/2370816.2370885},
     doi = {10.1145/2370816.2370885},
     acmid = {2370885},
     publisher = {ACM},
     keywords = {hardware transactional memory, on-chip network},
    }

2011

  • [DOI] W. Choi and J. Draper, “Implementation of unified signatures for transactional memory systems,” in Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on, 2011, pp. 1-4.
    [Bibtex]
    @INPROCEEDINGS{6026349,
    author={Woojin Choi and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on}, title={Implementation of unified signatures for transactional memory systems},
    year={2011},
    month={aug.},
    volume={},
    number={},
    pages={1 -4},
    keywords={TM systems;hardware resources;hardware signatures;read signature;transactional memory systems;unified signatures;write signature;parallel programming;},
    doi={10.1109/MWSCAS.2011.6026349},
    ISSN={1548-3746},}
  • [DOI] M. Haghi and J. Draper, “Single-event transient mitigation in sub-micron combinational circuits,” in Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on, 2011, pp. 1-4.
    [Bibtex]
    @INPROCEEDINGS{6026599,
    author={Haghi, M. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on}, title={Single-event transient mitigation in sub-micron combinational circuits},
    year={2011},
    month={aug.},
    volume={},
    number={},
    pages={1 -4},
    keywords={2D TCAD simulations;SET pulse width;combinational logic;cross-coupled inverters;single-event transient mitigation;size 65 nm;submicron combinational circuits;weak latch;combinational circuits;},
    doi={10.1109/MWSCAS.2011.6026599},
    ISSN={1548-3746},}
  • [DOI] M. Haghi and J. Draper, “Comparison of charge sharing reduction techniques in deep sub-micron CMOS processes,” in Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on, 2011, pp. 1-4.
    [Bibtex]
    @INPROCEEDINGS{6026598,
    author={Haghi, M. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on}, title={Comparison of charge sharing reduction techniques in deep sub-micron CMOS processes},
    year={2011},
    month={aug.},
    volume={},
    number={},
    pages={1 -4},
    keywords={DTI;LET strength;NFET transistor;STI;Synopsys 2-D TCAD mixed-mode simulation;charge sharing reduction technique;deep submicron CMOS process;deep trench isolation;different nodal separation;guard-diode;guard-ring;heavy-ion particle;linear energy transfer;pulse broadening;shallow trench isolation;size 65 nm;CMOS integrated circuits;field effect transistors;isolation technology;technology CAD (electronics);},
    doi={10.1109/MWSCAS.2011.6026598},
    ISSN={1548-3746},}
  • [DOI] W. Choi and J. Draper, “Unified Signatures for Improving Performance in Transactional Memory,” in Parallel Distributed Processing Symposium (IPDPS), 2011 IEEE International, 2011, pp. 817-827.
    [Bibtex]
    @INPROCEEDINGS{6012891,
    author={Woojin Choi and Draper, J.},
    booktitle={Parallel Distributed Processing Symposium (IPDPS), 2011 IEEE International}, title={Unified Signatures for Improving Performance in Transactional Memory},
    year={2011},
    month={may},
    volume={},
    number={},
    pages={817 -827},
    keywords={TM system;concurrent transaction;conflict detection;hardware signature;parallel program;programmer productivity;read-access;read-signature;signature design;signature quality;signature size;transactional memory;unified signature;write-access;write-signature;concurrency control;parallel programming;storage management;transaction processing;},
    doi={10.1109/IPDPS.2011.81},
    ISSN={1530-2075},}

2010

  • [DOI] A. Deshpande and J. Draper, “Squaring units and a comparison with multipliers,” in Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on, 2010, pp. 1266-1269.
    [Bibtex]
    @INPROCEEDINGS{5548763,
    author={Deshpande, A. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on}, title={Squaring units and a comparison with multipliers},
    year={2010},
    month={aug.},
    volume={},
    number={},
    pages={1266 -1269},
    keywords={Radix-4 modified booth encoding;VLSI design;general-purpose multipliers;squaring units;VLSI;floating point arithmetic;multiplying circuits;},
    doi={10.1109/MWSCAS.2010.5548763},
    ISSN={1548-3746},}
  • [DOI] B. Zafar, J. Draper, and T. M. Pinkston, “Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip,” in Parallel Processing (ICPP), 2010 39th International Conference on, 2010, pp. 443-452.
    [Bibtex]
    @INPROCEEDINGS{5599186,
    author={Zafar, B. and Draper, J. and Pinkston, T.M.},
    booktitle={Parallel Processing (ICPP), 2010 39th International Conference on},
    title={Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip},
    year={2010},
    month={sept.},
    volume={},
    number={},
    pages={443 -452},
    keywords={2D network;cRing topologies;chip multiprocessors;cubic ring networks;network bandwidth;network load;network traffic;network-on-chip;on-chip network power;polymorphic topology;routing algorithm;multiprocessing systems;network-on-chip;},
    doi={10.1109/ICPP.2010.52},
    ISSN={0190-3918},}
  • K. Young Hoon and D. Jeff, “Fault-Tolerant Flow Control for Control Circuitry in On-Chip Routers,” in TECHCON, 2010.
    [Bibtex]
    @INPROCEEDINGS{techcon_young,
    author={Young Hoon, Kang and Jeff, Draper},
    booktitle={TECHCON},
    title={Fault-Tolerant Flow Control for Control Circuitry in On-Chip Routers},
    year={2010}, }
  • [DOI] A. Deshpande and J. Draper, “Squaring units and a comparison with multipliers,” in Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on, 2010, pp. 1266-1269.
    [Bibtex]
    @INPROCEEDINGS{5548763,
    author={Deshpande, A. and Draper, J.},
    booktitle={Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on},
    title={Squaring units and a comparison with multipliers},
    year={2010},
    month={aug.},
    volume={},
    number={},
    pages={1266 -1269},
    keywords={Radix-4 modified booth encoding;VLSI design;general-purpose multipliers;squaring units;VLSI;floating point arithmetic;multiplying circuits;},
    doi={10.1109/MWSCAS.2010.5548763},
    ISSN={1548-3746},}
  • [DOI] M. Haghi and J. Draper, “A single-event upset hardening technique for high speed MOS Current Mode Logic,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 4137-4140.
    [Bibtex]
    @INPROCEEDINGS{5537603,
    author={Haghi, M. and Draper, J.},
    booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
    title={A single-event upset hardening technique for high speed MOS Current Mode Logic},
    year={2010},
    month={30 2010-june 2},
    volume={},
    number={},
    pages={4137 -4140},
    keywords={MCML sequential element;flip-flops;frequency 4 GHz;high speed communication systems;high-speed MOS current mode logic;latches;single-event upset hardening technique;size 65 nm;MOS logic circuits;current-mode logic;flip-flops;logic design;sequential circuits;},
    doi={10.1109/ISCAS.2010.5537603},
    ISSN={},}
  • [DOI] W. Choi, Y. H. Kang, T. Kwon, and J. Draper, “Implementation of adaptive grain signatures for transactional memories,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 3489-3492.
    [Bibtex]
    @INPROCEEDINGS{5537831,
    author={Woojin Choi and Young Hoon Kang and Taek-Jun Kwon and Draper, J.},
    booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
    title={Implementation of adaptive grain signatures for transactional memories},
    year={2010},
    month={30 2010-june 2},
    volume={},
    number={},
    pages={3489 -3492},
    keywords={Verilog HDL implementation;adaptive grain signatures;architecture-level simulation;conflict detection;false positives;hardware signatures;marginal area overhead;transactional memory systems;hardware description languages;memory architecture;},
    doi={10.1109/ISCAS.2010.5537831},
    ISSN={},}
  • [DOI] Y. H. Kang, T. Kwon, and J. Draper, “Fault-Tolerant Flow Control in On-chip Networks,” in Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, 2010, pp. 79-86.
    [Bibtex]
    @INPROCEEDINGS{5507558,
    author={Young Hoon Kang and Taek-Jun Kwon and Draper, J.},
    booktitle={Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on},
    title={Fault-Tolerant Flow Control in On-chip Networks},
    year={2010},
    month={may},
    volume={},
    number={},
    pages={79 -86},
    keywords={TSMC standard cell library;chip multiprocessors;dynamic packet fragmentation;fault handling techniques;fault-containment;fault-tolerant flow control;faulty flit transmission;interconnection network;link-level retransmission;on-chip networks;router;size 45 nm;triple modular redundancy;fault tolerant computing;multiprocessing systems;network routing;network-on-chip;},
    doi={10.1109/NOCS.2010.18},
    ISSN={},}
  • [DOI] W. Choi and J. Draper, “Locality-aware adaptive grain signatures for Transactional Memories,” in Parallel Distributed Processing (IPDPS), 2010 IEEE International Symposium on, 2010, pp. 1-10.
    [Bibtex]
    @INPROCEEDINGS{5470476,
    author={Woojin Choi and Draper, J.},
    booktitle={Parallel Distributed Processing (IPDPS), 2010 IEEE International Symposium on},
    title={Locality-aware adaptive grain signatures for Transactional Memories},
    year={2010},
    month={april},
    volume={},
    number={},
    pages={1 -10},
    keywords={area-efficient mechanism;conflict detection;hardware signature;locality-aware adaptive grain signature;transactional memory;parallel processing;storage management;transaction processing;},
    doi={10.1109/IPDPS.2010.5470476},
    ISSN={1530-2075},}

2009

  • [DOI] T. Kwon and J. Draper, “Floating-point division and square root using a Taylor-series expansion algorithm,” Microelectronics Journal, vol. 40, iss. 11, pp. 1601-1605, 2009.
    [Bibtex]
    @article{Kwon20091601,
    title = "Floating-point division and square root using a Taylor-series expansion algorithm",
    journal = "Microelectronics Journal",
    volume = "40",
    number = "11",
    pages = "1601 - 1605",
    year = "2009",
    note = "International Conference on Microelectronics Digital and Mixed-Signal Circuits and Systems",
    issn = "0026-2692",
    doi = "10.1016/j.mejo.2009.03.004",
    url = "http://www.sciencedirect.com/science/article/pii/S0026269209000500",
    author = "Taek-Jun Kwon and Jeffrey Draper",
    keywords = "Floating-point unit",
    keywords = "Division",
    keywords = "Square root"
    }
  • [DOI] M. Haghi and J. Draper, “The 90 nm Double-DICE storage element to reduce Single-Event upsets,” in Circuits and Systems, 2009. MWSCAS ’09. 52nd IEEE International Midwest Symposium on, 2009, pp. 463-466.
    [Bibtex]
    @INPROCEEDINGS{5236054,
    author={Haghi, M. and Draper, J.},
    booktitle={Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on},
    title={The 90 nm Double-DICE storage element to reduce Single-Event upsets},
    year={2009},
    month={aug.},
    volume={},
    number={},
    pages={463 -466},
    keywords={charge collecting;double-DICE storage element;dual interlocked cell storage cell;sensitive nodes;single-event strike;single-event upsets;size 5 mum;size 8.5 mum;size 90 nm;storage management chips;},
    doi={10.1109/MWSCAS.2009.5236054},
    ISSN={1548-3746},}
  • [DOI] Y. H. Kang, J. Sondeen, and J. Draper, “Implementing tree-based multicast routing for write invalidation messages in networks-on-chip,” in Circuits and Systems, 2009. MWSCAS ’09. 52nd IEEE International Midwest Symposium on, 2009, pp. 1118-1121.
    [Bibtex]
    @INPROCEEDINGS{5235964,
    author={Young Hoon Kang and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on},
    title={Implementing tree-based multicast routing for write invalidation messages in networks-on-chip},
    year={2009},
    month={aug.},
    volume={},
    number={},
    pages={1118 -1121},
    keywords={bit-string multidestination encoding;directory-based protocol;distributed shared memory system;dual-path router;energy consumption;network traffic;networks-on-chip;single-flit write invalidation message;size 90 nm;tree-based multicast routing;tree-based write invalidation router;unicast router;write invalidation transaction;distributed shared memory systems;network routing;network-on-chip;protocols;trees (mathematics);},
    doi={10.1109/MWSCAS.2009.5235964},
    ISSN={1548-3746},}
  • [DOI] Y. H. Kang, T. Kwon, and J. Draper, “Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers,” in Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on, 2009, pp. 250-255.
    [Bibtex]
    @INPROCEEDINGS{5071474,
    author={Young Hoon Kang and Taek-Jun Kwon and Draper, J.},
    booktitle={Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on},
    title={Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers},
    year={2009},
    month={may},
    volume={},
    number={},
    pages={250 -255},
    keywords={congestion propagation effect;dynamic packet fragmentation;on-chip routers;virtual channel utilization;buffer circuits;network-on-chip;telecommunication network routing;},
    doi={10.1109/NOCS.2009.5071474},
    ISSN={},}
  • [DOI] M. Haghi and J. Draper, “The effect of design parameters on single-event upset sensitivity of MOS current mode logic,” in Proceedings of the 19th ACM Great Lakes symposium on VLSI, New York, NY, USA, 2009, pp. 233-238.
    [Bibtex]
    @inproceedings{Haghi:2009:EDP:1531542.1531599,
     author = {Haghi, Mahta and Draper, Jeff},
     title = {The effect of design parameters on single-event upset sensitivity of MOS current mode logic},
     booktitle = {Proceedings of the 19th ACM Great Lakes symposium on VLSI},
     series = {GLSVLSI '09},
     year = {2009},
     isbn = {978-1-60558-522-2},
     location = {Boston Area, MA, USA},
     pages = {233--238},
     numpages = {6},
     url = {http://doi.acm.org/10.1145/1531542.1531599},
     doi = {http://doi.acm.org/10.1145/1531542.1531599},
     acmid = {1531599},
     publisher = {ACM},
     address = {New York, NY, USA},
     keywords = {design parameters, mos current mode logic (mcml), radiation hardening, single event upset (seu)},
    }
  • [DOI] Y. H. Kang, J. Sondeen, and J. Draper, “Multicast routing with dynamic packet fragmentation,” in Proceedings of the 19th ACM Great Lakes symposium on VLSI, New York, NY, USA, 2009, pp. 113-116.
    [Bibtex]
    @inproceedings{Kang:2009:MRD:1531542.1531571,
     author = {Kang, Young Hoon and Sondeen, Jeff and Draper, Jeff},
     title = {Multicast routing with dynamic packet fragmentation},
     booktitle = {Proceedings of the 19th ACM Great Lakes symposium on VLSI},
     series = {GLSVLSI '09},
     year = {2009},
     isbn = {978-1-60558-522-2},
     location = {Boston Area, MA, USA},
     pages = {113--116},
     numpages = {4},
     url = {http://doi.acm.org/10.1145/1531542.1531571},
     doi = {http://doi.acm.org/10.1145/1531542.1531571},
     acmid = {1531571},
     publisher = {ACM},
     address = {New York, NY, USA},
     keywords = {NoC, interconnection network, on-chip router},
    }

2008

  • [DOI] R. Naseer and J. Draper, “Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs,” in Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, 2008, pp. 222-225.
    [Bibtex]
    @INPROCEEDINGS{4681832,
    author={Naseer, R. and Draper, J.},
    booktitle={Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European},
    title={Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs},
    year={2008},
    month={sept.},
    volume={},
    number={},
    pages={222 -225},
    keywords={ECC implementation technique;SEC-DED error-correcting codes;SRAM multibit upset;double-error correcting;irradiation tests;parallel double error correcting code;size 90 nm;SRAM chips;error correction codes;integrated circuit testing;radiation hardening (electronics);},
    doi={10.1109/ESSCIRC.2008.4681832},
    ISSN={1930-8833},}
  • [DOI] T. Kwon, J. Sondeen, and J. Draper, “Floating-point division and square root implementation using a Taylor-series expansion algorithm,” in Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on, 2008, pp. 702-705.
    [Bibtex]
    @INPROCEEDINGS{4674950,
    author={Taek-Jun Kwon and Sondeen, J. and Draper, J.},
    booktitle={Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on},
    title={Floating-point division and square root implementation using a Taylor-series expansion algorithm},
    year={2008},
    month={31 2008-sept. 3},
    volume={},
    number={},
    pages={702 -705},
    keywords={Taylor-series expansion algorithm;VLSI;arithmetic unit;floating-point division;square root implementation;standard cell methodology;VLSI;floating point arithmetic;series (mathematics);},
    doi={10.1109/ICECS.2008.4674950},
    ISSN={},}
  • [DOI] R. Naseer and J. Draper, “DEC ECC design to improve memory reliability in Sub-100nm technologies,” in Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on, 2008, pp. 586-589.
    [Bibtex]
    @INPROCEEDINGS{4674921,
    author={Naseer, R. and Draper, J.},
    booktitle={Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on},
    title={DEC ECC design to improve memory reliability in Sub-100nm technologies},
    year={2008},
    month={31 2008-sept. 3},
    volume={},
    number={},
    pages={586 -589},
    keywords={90nm ASIC technology;DEC ECC design;SRAM reliability;double error correcting BCH codes;error correcting codes;exacerbated SRAM reliability;iterative decoding algorithms;memory word widths;parallel decoding implementation;size 90 nm;sub-100nm technology;word length 16 bit;word length 64 bit;SRAM chips;error correction codes;integrated circuit reliability;iterative decoding;},
    doi={10.1109/ICECS.2008.4674921},
    ISSN={},}
  • N. Riaz, B. Younes, B. A. Michael, J. Sondeen, S. D. Scott, and D. Jeff, “Single-Event Effects Characterization and Soft Error Mitigation in 90nm Commercial-Density SRAMs,” in the IASTED International Conference on Circuits and Systems, 2008, pp. 153-158.
    [Bibtex]
    @INPROCEEDINGS{4674922,
    author={Riaz,Naseer and Younes, Boulghassoul and Michael, A. Bajura and Jeff Sondeen and Scott, D. Stansberry and Jeff, Draper},
    booktitle={the IASTED International Conference on Circuits and Systems},
    title={Single-Event Effects Characterization and Soft Error Mitigation in 90nm Commercial-Density SRAMs},
    year={2008},
    month={August},
    volume={},
    number={},
    pages={153 - 158}, }
  • [DOI] T. J. Kwon and J. Draper, “Floating-point division and square root implementation using a Taylor-series expansion algorithm with reduced look-up tables,” in Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on, 2008, pp. 954-957.
    [Bibtex]
    @INPROCEEDINGS{4616959,
    author={Taek Jun Kwon and Draper, J.},
    booktitle={Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on},
    title={Floating-point division and square root implementation using a Taylor-series expansion algorithm with reduced look-up tables},
    year={2008},
    month={aug.},
    volume={},
    number={},
    pages={954 -957},
    keywords={IBM;Taylor-series expansion algorithm;floating-point arithmetic;floating-point division;look-up tables;microprocessor design;size 90 nm;square root function;square root implementation;floating point arithmetic;microprocessor chips;table lookup;},
    doi={10.1109/MWSCAS.2008.4616959},
    ISSN={1548-3746},}
  • [DOI] Y. H. Kang and J. Draper, “Precise exception handling in discontinuous control flow scenarios for area-constrained systems,” in Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on, 2008, pp. 527-530.
    [Bibtex]
    @INPROCEEDINGS{4616852,
    author={Young Hoon Kang and Draper, J.},
    booktitle={Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on},
    title={Precise exception handling in discontinuous control flow scenarios for area-constrained systems},
    year={2008},
    month={aug.},
    volume={},
    number={},
    pages={527 -530},
    keywords={area-constrained systems;discontinuous control flow scenarios;discrete control flow;embedded systems;hardware resource;pipelined processors;precise exception handling;processing-in-memory systems;size 90 nm;embedded systems;exception handling;microprocessor chips;pipeline processing;},
    doi={10.1109/MWSCAS.2008.4616852},
    ISSN={1548-3746},}

2007

  • [DOI] M. A. Bajura, Y. Boulghassoul, R. Naseer, S. DasGupta, A. F. Witulski, J. Sondeen, S. D. Stansberry, J. Draper, L. W. Massengill, and J. N. Damoulakis, “Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs,” Nuclear Science, IEEE Transactions on, vol. 54, iss. 4, pp. 935-945, 2007.
    [Bibtex]
    @ARTICLE{4291685,
    author={Bajura, M.A. and Boulghassoul, Y.. and Naseer, R.. and DasGupta, S.. and Witulski, A.F. and Sondeen, J.. and Stansberry, S.D. and Draper, J.. and Massengill, L.W. and Damoulakis, J.N.},
    journal={Nuclear Science, IEEE Transactions on},
    title={Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs},
    year={2007},
    month={aug. },
    volume={54},
    number={4},
    pages={935 -945},
    keywords={SRAM memory cells;bit error rate model;memory fault tolerance;memory scrubbing rate;radiation effects;single-bit-correcting error-correcting codes;triple-bit-correcting error-correcting codes;SRAM chips;error correction codes;error statistics;radiation effects;},
    doi={10.1109/TNS.2007.892119},
    ISSN={0018-9499},}
  • [DOI] T. Kwon, J. Sondeen, and J. Draper, “Floating-point division and square root using a Taylor-series expansion algorithm,” in Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, 2007, pp. 305-308.
    [Bibtex]
    @INPROCEEDINGS{4488594,
    author={Taek-Jun Kwon and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on},
    title={Floating-point division and square root using a Taylor-series expansion algorithm},
    year={2007},
    month={aug.},
    volume={},
    number={},
    pages={305 -308},
    keywords={FP-div units;FP-sqrt units;Taylor theorem;Taylor-series expansion algorithm;floating-point arithmetic;floating-point division;fused floating-point divide;fused floating-point multiply;fused floating-point square root;microprocessor design;square root function;floating point arithmetic;integrated circuit design;microprocessor chips;},
    doi={10.1109/MWSCAS.2007.4488594},
    ISSN={1548-3746},}
  • [DOI] Y. H. Kang and J. Draper, “Design trade-offs for load/store buffers in embedded processing environments,” in Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, 2007, pp. 1461-1464.
    [Bibtex]
    @INPROCEEDINGS{4488819,
    author={Young Hoon Kang and Draper, J.},
    booktitle={Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on},
    title={Design trade-offs for load/store buffers in embedded processing environments},
    year={2007},
    month={aug.},
    volume={},
    number={},
    pages={1461 -1464},
    keywords={chip multiprocessing systems;design trade-offs;embedded processing;load/store queue;memory latency;scalar load-store buffer;wideword load-store buffer;buffer storage;microprocessor chips;multiprocessing systems;},
    doi={10.1109/MWSCAS.2007.4488819},
    ISSN={1548-3746},}
  • [DOI] R. Z. Bhatti, M. Denneau, and J. Draper, “Data strobe timing of DDR2 using a statistical random sampling technique,” in Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, 2007, pp. 1114-1117.
    [Bibtex]
    @INPROCEEDINGS{4488753,
    author={Bhatti, R.Z. and Denneau, M. and Draper, J.},
    booktitle={Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on},
    title={Data strobe timing of DDR2 using a statistical random sampling technique},
    year={2007},
    month={aug.},
    volume={},
    number={},
    pages={1114 -1117},
    keywords={FPGA technologies;Samsung K4T51163QB_D5 DDR2 chips;data strobe timing;parallel processing logic ASIC chip;standard cell based design;statistical random sampling technique;synchronous signals;application specific integrated circuits;field programmable gate arrays;parallel processing;random processes;statistical analysis;},
    doi={10.1109/MWSCAS.2007.4488753},
    ISSN={1548-3746},}
  • [DOI] R. Z. Bhatti, K. M. Chugg, and J. Draper, “Standard cell based pseudo-random clock generator for statistical random sampling of digital signals,” in Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on, 2007, pp. 1110-1113.
    [Bibtex]
    @INPROCEEDINGS{4488752,
    author={Bhatti, R.Z. and Chugg, K.M. and Draper, J.},
    booktitle={Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on},
    title={Standard cell based pseudo-random clock generator for statistical random sampling of digital signals},
    year={2007},
    month={aug.},
    volume={},
    number={},
    pages={1110 -1113},
    keywords={circuit design technique;digital signals;elegant design-time efficient technique;on-chip integration;periodic cycles;pseudo-random clock generator;standard cell;statistical random sampling;uniformly distributed sampling;VLSI;clocks;digital integrated circuits;signal sampling;statistical analysis;timing circuits;},
    doi={10.1109/MWSCAS.2007.4488752},
    ISSN={1548-3746},}
  • [DOI] S. D. Mediratta and J. Draper, “Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router,” in Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on, 2007, pp. 69-75.
    [Bibtex]
    @INPROCEEDINGS{4429960,
    author={Mediratta, S.D. and Draper, J.},
    booktitle={Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on},
    title={Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router},
    year={2007},
    month={july},
    volume={},
    number={},
    pages={69 -75},
    keywords={fault-tolerance;generic fault-tolerant routing algorithm;multi-core architectures;next generation VLSI;path exploration;probe-send fault-tolerant network-on-chip router;system-on-chip;VLSI;fault tolerance;network-on-chip;reliability;},
    doi={10.1109/ASAP.2007.4429960},
    ISSN={},}
  • [DOI] R. Naseer, Y. Boulghassoul, J. Draper, S. DasGupta, and A. Witulski, “Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM,” in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2007, pp. 1879-1882.
    [Bibtex]
    @INPROCEEDINGS{4253029,
    author={Naseer, R. and Boulghassoul, Y. and Draper, J. and DasGupta, S. and Witulski, A.},
    booktitle={Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on},
    title={Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM},
    year={2007},
    month={may},
    volume={},
    number={},
    pages={1879 -1882},
    keywords={90 nm;SRAM chips;current pulse modeling;nodal capacitances;soft error rate;static random access memories;SRAM chips;radiation hardening (electronics);technology CAD (electronics);},
    doi={10.1109/ISCAS.2007.378282},
    ISSN={},}
  • [DOI] S. D. Mediratta and J. Draper, “Characterization of a Fault-tolerant NoC Router,” in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2007, pp. 381-384.
    [Bibtex]
    @INPROCEEDINGS{4252651,
    author={Mediratta, S.D. and Draper, J.},
    booktitle={Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on},
    title={Characterization of a Fault-tolerant NoC Router},
    year={2007},
    month={may},
    volume={},
    number={},
    pages={381 -384},
    keywords={IBM Cu-08 technology;VLSI technologies;data communication;fault detection;fault-tolerant NoC router;k-ary 2-cube torus router;multicore architectures;network-on-chips;reliability;system reconfiguration;system-on-chip;VLSI;data communication;fault tolerance;network-on-chip;},
    doi={10.1109/ISCAS.2007.378469},
    ISSN={},}
  • [DOI] R. Naseer, J. Draper, Y. Boulghassoul, S. DasGupta, and A. Witulski, “Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology,” in Proceedings of the 17th ACM Great Lakes symposium on VLSI, New York, NY, USA, 2007, pp. 227-230.
    [Bibtex]
    @inproceedings{Naseer:2007:CCS:1228784.1228843,
     author = {Naseer, Riaz and Draper, Jeff and Boulghassoul, Younes and DasGupta, Sandeepan and Witulski, Art},
     title = {Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology},
     booktitle = {Proceedings of the 17th ACM Great Lakes symposium on VLSI},
     series = {GLSVLSI '07},
     year = {2007},
     isbn = {978-1-59593-605-9},
     location = {Stresa-Lago Maggiore, Italy},
     pages = {227--230},
     numpages = {4},
     url = {http://doi.acm.org/10.1145/1228784.1228843},
     doi = {http://doi.acm.org/10.1145/1228784.1228843},
     acmid = {1228843},
     publisher = {ACM},
     address = {New York, NY, USA},
     keywords = {critical charge, single event transient, soft error},
    }

2006

  • M. Sumit and D. Jeffrey, “Achieving On-chip Fault-tolerance Utilizing BIST Resources,” WSEAS Transactions on Circuits and Systems, vol. 5, iss. 12, pp. 1726-33, 2006.
    [Bibtex]
    @ARTICLE{BIST,
    author={Sumit, Mediratta and Jeffrey, Draper},
    journal={WSEAS Transactions on Circuits and Systems},
    title={Achieving On-chip Fault-tolerance Utilizing BIST Resources},
    year={2006},
    month={Dec},
    volume={5},
    number={12},
    pages={1726 -33}, }
  • S. D. Mediratta and J. Draper, “Effective realization of on-chip fault-tolerance utilizing BIST resources,” in Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing, Stevens Point, Wisconsin, USA, 2006, pp. 215-220.
    [Bibtex]
    @inproceedings{Mediratta:2006:ERO:1376148.1376188,
     author = {Mediratta, Sumit Dharampal and Draper, Jeffrey},
     title = {Effective realization of on-chip fault-tolerance utilizing BIST resources},
     booktitle = {Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control \& Signal Processing},
     year = {2006},
     isbn = {960-8457-55-6},
     location = {Dallas, Texas},
     pages = {215--220},
     numpages = {6},
     url = {http://dl.acm.org/citation.cfm?id=1376148.1376188},
     acmid = {1376188},
     publisher = {World Scientific and Engineering Academy and Society (WSEAS)},
     address = {Stevens Point, Wisconsin, USA},
     keywords = {built-in-self-test (BIST), multi-core, on-chip fault-tolerance, reliability, system-on-chip},
    }
  • [DOI] R. Naseer, R. Z. Bhatti, and J. Draper, “Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology,” in Circuits and Systems, 2006. MWSCAS ’06. 49th IEEE International Midwest Symposium on, 2006, pp. 515-519.
    [Bibtex]
    @INPROCEEDINGS{4267189,
    author={Naseer, Riaz and Bhatti, Rashed Zafar and Draper, Jeff},
    booktitle={Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on},
    title={Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology},
    year={2006},
    month={aug.},
    volume={1},
    number={},
    pages={515 -519},
    keywords={},
    doi={10.1109/MWSCAS.2006.382112},
    ISSN={1548-3746},}
  • [DOI] S. D. Mediratta and J. Draper, “On-chip Fault-tolerance Utilizing BIST Resources,” in Circuits and Systems, 2006. MWSCAS ’06. 49th IEEE International Midwest Symposium on, 2006, pp. 254-258.
    [Bibtex]
    @INPROCEEDINGS{4267337,
    author={Mediratta, S.D. and Draper, J.},
    booktitle={Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on},
    title={On-chip Fault-tolerance Utilizing BIST Resources},
    year={2006},
    month={aug.},
    volume={2},
    number={},
    pages={254 -258},
    keywords={BIST resources;International Technology Roadmap for Semiconductors;VLSI chip lifetime;VLSI fabrication technology;built-in-self-test resources;on-chip fault-tolerance analysis;post-fabrication reconfigurability;production cost reduction;productivity;reliability challenges;reusability aspects;size 65 nm;time-to-market;yield enhancement;VLSI;built-in self test;cost reduction;fault tolerance;integrated circuit reliability;integrated circuit testing;integrated circuit yield;productivity;time to market;},
    doi={10.1109/MWSCAS.2006.382259},
    ISSN={1548-3746},}
  • [DOI] R. Z. Bhatti, C. Steele, and J. Draper, “PBuf: An On-Chip Packet Transfer Engine for MONARCH,” in Circuits and Systems, 2006. MWSCAS ’06. 49th IEEE International Midwest Symposium on, 2006, pp. 531-535.
    [Bibtex]
    @INPROCEEDINGS{4267408,
    author={Bhatti, R.Z. and Steele, C. and Draper, J.},
    booktitle={Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on},
    title={PBuf: An On-Chip Packet Transfer Engine for MONARCH},
    year={2006},
    month={aug.},
    volume={2},
    number={},
    pages={531 -535},
    keywords={MONARCH;PBuf;address space boundaries;address translation process;data transfer capabilities;memory to memory block transfer engines;morphable networked microarchitecture;node interconnection;on-chip packet interface/router;on-chip packet switching router;on-chip packet transfer engine;packet buffer design;buffer storage;integrated circuit design;integrated circuit interconnections;microprocessor chips;network routing;},
    doi={10.1109/MWSCAS.2006.381784},
    ISSN={1548-3746},}
  • [DOI] R. Naseer and J. Draper, “DF-DICE: a scalable solution for soft error tolerant circuit design,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, p. 4 pp..
    [Bibtex]
    @INPROCEEDINGS{1693478,
    author={Naseer, R. and Draper, J.},
    booktitle={Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on},
    title={DF-DICE: a scalable solution for soft error tolerant circuit design},
    year={2006},
    month={may},
    volume={},
    number={},
    pages={4 pp.},
    keywords={ASIC;DF-DICE;application specific integrated circuit;delay filtered dual interlocked storage cell;flip-flops;radiation environments;single event transient thresholds;soft error mitigation;soft error tolerant circuit;space environment;application specific integrated circuits;circuit stability;fault tolerance;flip-flops;integrated circuit reliability;radiation hardening (electronics);},
    doi={10.1109/ISCAS.2006.1693478},
    ISSN={},}
  • [DOI] R. Z. Bhatti, M. Denneau, and J. Draper, “Phase measurement and adjustment of digital signals using random sampling technique,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, p. 4 pp..
    [Bibtex]
    @INPROCEEDINGS{1693477,
    author={Bhatti, R.Z. and Denneau, M. and Draper, J.},
    booktitle={Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on},
    title={Phase measurement and adjustment of digital signals using random sampling technique},
    year={2006},
    month={may},
    volume={},
    number={},
    pages={4 pp.},
    keywords={130 nm;circuit complexity;digital signal adjustment;digital system signaling;inferential statistic;on-chip high speed digital signal;phase measurement;random sampling technique;random sampling unit circuit;relative phase;timing uncertainty mitigation;phase estimation;phase measurement;signal processing equipment;signal sampling;},
    doi={10.1109/ISCAS.2006.1693477},
    ISSN={},}
  • [DOI] T. Barrett, S. Mediratta, T. Kwon, R. Singh, S. Chandra, J. Sondeen, and J. Draper, “A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, p. 4 pp..
    [Bibtex]
    @INPROCEEDINGS{1692989,
    author={Barrett, T. and Sumit Mediratta and Taek-Jun Kwon and Ravinder Singh and Sachit Chandra and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on},
    title={A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability},
    year={2006},
    month={may},
    volume={},
    number={},
    pages={4 pp.},
    keywords={0.18 micron;HP zx6000 workstation;PIM chip;PIM computing;PIM device;SDRAM interface;TSMC;data-intensive architecture;double-data rate;floating-point unit;processing-in-memory;smart-memory coprocessors;wideword floating-point capability;wideword pipeline;DRAM chips;coprocessors;floating point arithmetic;integrated circuit design;},
    doi={10.1109/ISCAS.2006.1692989},
    ISSN={},}
  • [DOI] R. Z. Bhatti, M. Denneau, and J. Draper, “2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology,” in Proceedings of the 16th ACM Great Lakes symposium on VLSI, New York, NY, USA, 2006, pp. 198-203.
    [Bibtex]
    @inproceedings{Bhatti:2006:GSD:1127908.1127956,
     author = {Bhatti, Rashed Zafar and Denneau, Monty and Draper, Jeff},
     title = {2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology},
     booktitle = {Proceedings of the 16th ACM Great Lakes symposium on VLSI},
     series = {GLSVLSI '06},
     year = {2006},
     isbn = {1-59593-347-6},
     location = {Philadelphia, PA, USA},
     pages = {198--203},
     numpages = {6},
     url = {http://doi.acm.org/10.1145/1127908.1127956},
     doi = {http://doi.acm.org/10.1145/1127908.1127956},
     acmid = {1127956},
     publisher = {ACM},
     address = {New York, NY, USA},
     keywords = {CDR, CML driver, DLL, LVDS, PLL, SerDes, duty cycle correction (DCC), jitter and skew compensation, phase detection, standard cell based serializer and deserializer circuits for high speed signaling},
    }

2005

  • [DOI] J. Draper, T. J. Barrett, J. Sondeen, S. Mediratta, C. W. Kang, I. Kim, and G. Daglikoca, “A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System,” J. VLSI Signal Process. Syst., vol. 40, pp. 73-84, 2005.
    [Bibtex]
    @article{Draper:2005:PP(:1050556.1050595,
     author = {Draper, Jaffrey and Barrett, J. Tim and Sondeen, Jeff and Mediratta, Sumit and Kang, Chang Woo and Kim, Ihn and Daglikoca, Gokhan},
     title = {A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System},
     journal = {J. VLSI Signal Process. Syst.},
     volume = {40},
     issue = {1},
     month = {May},
     year = {2005},
     issn = {0922-5773},
     pages = {73--84},
     numpages = {12},
     url = {http://dl.acm.org/citation.cfm?id=1050556.1050595},
     doi = {10.1007/s11265-005-4939-1},
     acmid = {1050595},
     publisher = {Kluwer Academic Publishers},
     address = {Hingham, MA, USA},
     keywords = {memory bandwidth, memory wall, processing-in-memory},
    }
  • S. D. Mediratta and J. T. Draper, “Performance Analysis of User-Level PIM Communication in the Data IntensiVe Architecture (DIVA) System.,” in HiPC’05, 2005, pp. 407-419.
    [Bibtex]
    @INPROCEEDINGS{ d. mediratta:performance,
    AUTHOR = "Sumit D. Mediratta and Jeffrey T. Draper",
    TITLE = "Performance Analysis of User-Level PIM Communication in the Data IntensiVe Architecture (DIVA) System.",
    booktitle = "HiPC'05",
    PAGES = {407-419},
    YEAR = {2005}  }
  • [DOI] R. Z. Bhatti, M. Denneau, and J. Draper, “Duty cycle measurement and correction using a random sampling technique,” in Circuits and Systems, 2005. 48th Midwest Symposium on, 2005, p. 1043 – 1046 Vol. 2.
    [Bibtex]
    @INPROCEEDINGS{1594283,
    author={Bhatti, R.Z. and Denneau, M. and Draper, J.},
    booktitle={Circuits and Systems, 2005. 48th Midwest Symposium on},
    title={Duty cycle measurement and correction using a random sampling technique},
    year={2005},
    month={aug.},
    volume={},
    number={},
    pages={ 1043 - 1046 Vol. 2},
    keywords={ DRAM; SERDES circuit; VLSI circuit; deserializer circuit; duty cycle correction; duty cycle measurement; dynamic-domino pipelined circuit; on-chip clock; pipelined analog-to-digital converter; random sampling technique; serializer circuit; VLSI; clocks; logic circuits; signal sampling;},
    doi={10.1109/MWSCAS.2005.1594283},
    ISSN={},}
  • [DOI] R. Naseer and J. Draper, “The DF-dice storage element for immunity to soft errors,” in Circuits and Systems, 2005. 48th Midwest Symposium on, 2005, p. 303 – 306 Vol. 1.
    [Bibtex]
    @INPROCEEDINGS{1594099,
    author={Naseer, R. and Draper, J.},
    booktitle={Circuits and Systems, 2005. 48th Midwest Symposium on},
    title={The DF-dice storage element for immunity to soft errors},
    year={2005},
    month={aug.},
    volume={},
    number={},
    pages={ 303 - 306 Vol. 1},
    keywords={ 800 ps; DF dice storage element; application specific integrated circuits; delay filtering; dual interlocked storage cell; single event upsets; single-event transients; soft error immunity; soft-error tolerant design; application specific integrated circuits; fault tolerance; integrated circuit reliability; integrated memory circuits; radiation effects;},
    doi={10.1109/MWSCAS.2005.1594099},
    ISSN={},}
  • [DOI] T. Kwon, J. Sondeen, and J. Draper, “Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005, p. 3331 – 3334 Vol. 4.
    [Bibtex]
    @INPROCEEDINGS{1465341,
    author={Taek-Jun Kwon and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on},
    title={Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems},
    year={2005},
    month={may},
    volume={},
    number={},
    pages={ 3331 - 3334 Vol. 4},
    keywords={ 0.18 micron; CMOS; FPU design trade-offs; add instructions; circuit optimization; concurrent execution; embedded systems; floating-point arithmetic; floating-point unit implementation; microprocessors; multiply instructions; processing-in-memory systems; single-instruction implementation; adders; circuit optimisation; embedded systems; floating point arithmetic; multiplying circuits;},
    doi={10.1109/ISCAS.2005.1465341},
    ISSN={},}
  • [DOI] S. D. Mediratta, C. Steele, J. Sondeen, and J. Draper, “An area-efficient and protected network interface for processing-in-memory systems,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005, p. 2951 – 2954 Vol. 3.
    [Bibtex]
    @INPROCEEDINGS{1465246,
    author={Mediratta, S.D. and Steele, C. and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on},
    title={An area-efficient and protected network interface for processing-in-memory systems},
    year={2005},
    month={may},
    volume={},
    number={},
    pages={ 2951 - 2954 Vol. 3},
    keywords={ 0.18 micron; 140 MHz; 32.30 mW; 48.08 Gbit/s; CMOS; DIVA PIM; aggregate bi-directional throughput; area-efficient interface; data intensive architecture; low area; low power consumption; memory-mapped network interface; parcel buffer; pbuf implementation; processing-in-memory systems; protected user network interface; CMOS digital integrated circuits; buffer storage; low-power electronics; network interfaces; storage management chips;},
    doi={10.1109/ISCAS.2005.1465246},
    ISSN={},}

2004

  • [DOI] S. Mediratta, C. Steele, R. Singh, J. Sondeen, and J. Draper, “A 0.18 mu;m CMOS implementation of an area efficient precise exception handling unit for processing-in-memory systems,” in Circuits and Systems, 2004. MWSCAS ’04. The 2004 47th Midwest Symposium on, 2004, p. III_455 – III_458.
    [Bibtex]
    @INPROCEEDINGS{1354393,
    author={Mediratta, S. and Steele, C. and Singh, R. and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on},
    title={A 0.18 mu;m CMOS implementation of an area efficient precise exception handling unit for processing-in-memory systems},
    year={2004},
    month={july},
    volume={3},
    number={},
    pages={ III_455 - III_458},
    keywords={},
    doi={10.1109/MWSCAS.2004.1354393},
    ISSN={ },}
  • [DOI] T. Kwon, J. Moon, J. Sondeen, and J. Draper, “A 0.18 mu;m implementation of a floating-point unit for a processing-in-memory system,” in Circuits and Systems, 2004. ISCAS ’04. Proceedings of the 2004 International Symposium on, 2004, p. II – 453-6 Vol.2.
    [Bibtex]
    @INPROCEEDINGS{1329306,
    author={Taek-Jun Kwon and Joong-Seok Moon and Sondeen, J. and Draper, J.},
    booktitle={Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on},
    title={A 0.18 mu;m implementation of a floating-point unit for a processing-in-memory system},
    year={2004},
    month={may},
    volume={2},
    number={},
    pages={ II - 453-6 Vol.2},
    keywords={ 0.18 micron; CMOS technology; IEEE-754 standard; block sharing; data intensive architecture system; hardware efficient division algorithm; microprocessor; parallel single precision floating point operations; processing in memory chips; smart memory coprocessors; standard cell methodology; CMOS integrated circuits; coprocessors; floating point arithmetic; microprocessor chips;},
    doi={10.1109/ISCAS.2004.1329306},
    ISSN={},}
  • [DOI] S. Mediratta, J. Sondeen, and J. Draper, “An area-efficient router for the Data-Intensive Architecture (DIVA) system,” in VLSI Design, 2004. Proceedings. 17th International Conference on, 2004, pp. 863-868.
    [Bibtex]
    @INPROCEEDINGS{1261039,
    author={Mediratta, S. and Sondeen, J. and Draper, J.},
    booktitle={VLSI Design, 2004. Proceedings. 17th International Conference on},
    title={An area-efficient router for the Data-Intensive Architecture (DIVA) system},
    year={2004},
    month={},
    volume={},
    number={},
    pages={ 863 - 868},
    keywords={ SRAM chips; coprocessors; data intensive architecture system; network routing; performance evaluation; processing in-memory chips; processing in-memory routing component; static random access storage; SRAM chips; coprocessors; memory architecture; network routing; parallel architectures; performance evaluation;},
    doi={10.1109/ICVD.2004.1261039},
    ISSN={ },}

2003

  • [DOI] J. Moon, W. C. Athas, S. D. Soli, J. T. Draper, and P. A. Beerel, “Voltage-pulse driven harmonic resonant rail drivers for low-power applications,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, iss. 5, pp. 762-777, 2003.
    [Bibtex]
    @ARTICLE{1234396,
    author={Joong-Seok Moon and Athas, W.C. and Soli, S.D. and Draper, J.T. and Beerel, P.A.},
    journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
    title={Voltage-pulse driven harmonic resonant rail drivers for low-power applications},
    year={2003},
    month={oct. },
    volume={11},
    number={5},
    pages={762 -777},
    keywords={0.8 to 15 MHz;38.3 to 97.8 pF;CMOS-VLSI systems;capacitive load;circuit implementation;circuit topology;clock frequency;consumed power minimization;current-fed voltage pulse-forming network theory;design technique;discrete passive components;energy-recovery circuit;external tuning;harmonic resonance;load capacitance;low-power applications;multiple harmonies;overall power dissipation;periodic 50% duty-cycle waveform;second-order harmonic rail driver;standard pulse source;trapezoidal-wave clock signal generation;voltage-pulse driven harmonic resonant rail drivers;CMOS analogue integrated circuits;driver circuits;integrated circuit design;low-power electronics;pulse circuits;waveform generators;},
    doi={10.1109/TVLSI.2003.814323},
    ISSN={1063-8210},}
  • H. Chiueh, J. Draper, and J. Choma, “A Dynamic Thermal Management Circuit for System-On-Chip Designs,” Analog Integrated Circuits and Signal Processing, vol. 36, pp. 175-181, 2003.
    [Bibtex]
    @article {springerlink:10.1023/A:1024430504653,
       author = {Chiueh, Herming and Draper, Jeffrey and Choma, John},
       affiliation = {Department of Communication Engineering National Chiao Tung University HsinChu 30050 Taiwan},
       title = {A Dynamic Thermal Management Circuit for System-On-Chip Designs},
       journal = {Analog Integrated Circuits and Signal Processing},
       publisher = {Springer Netherlands},
       issn = {0925-1030},
       keyword = {Engineering},
       pages = {175-181},
       volume = {36},
       issue = {1},
       url = {http://dx.doi.org/10.1023/A:1024430504653},
       note = {10.1023/A:1024430504653},
       year = {2003}
    }
  • [DOI] J. Moon, T. Kwon, J. Sondeen, and J. Draper, “An area-efficient standard-cell floating-point unit design for a processing-in-memory system,” in Solid-State Circuits Conference, 2003. ESSCIRC ’03. Proceedings of the 29th European, 2003, pp. 57-60.
    [Bibtex]
    @INPROCEEDINGS{1257071,
    author={Joong-Seok Moon and Taek-Jun Kwon and Sondeen, J. and Draper, J.},
    booktitle={Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European},
    title={An area-efficient standard-cell floating-point unit design for a processing-in-memory system},
    year={2003},
    month={sept.},
    volume={},
    number={},
    pages={ 57 - 60},
    keywords={ 0.18 microns; CMOS technology; IEEE-754 compliant; area-efficient floating-point design; bandwidth-limited applications; data-intensive architecture system; floating-point operations; hardware-efficient division algorithm; microprocessor; pipeline scheduling; processing-in-memory system; smart-memory coprocessors; standard cell methodology; standard-cell floating-point unit design; wideword floating-point computation; CMOS memory circuits; IEEE standards; coprocessors; floating point arithmetic;},
    doi={10.1109/ESSCIRC.2003.1257071},
    ISSN={ },}

2002

  • J. Draper, J. Sondeen, and C. W. Kang, “Implementation of a 256-bit wideword processor for the data-intensive architecture (DIVA) processing-in-memory (PIM) chip,” in Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European, 2002, pp. 77-80.
    [Bibtex]
    @INPROCEEDINGS{1471470,
    author={Draper, J. and Sondeen, J. and Chang Woo Kang},
    booktitle={Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European},
    title={Implementation of a 256-bit wideword processor for the data-intensive architecture (DIVA) processing-in-memory (PIM) chip},
    year={2002},
    month={sept.},
    volume={},
    number={},
    pages={77 -80},
    keywords={},
    doi={},
    ISSN={},}
  • H. Chiueh, J. Draper, S. Mediratta, and J. Sondeen, “The address translation unit of the data amp;#8211;intensive architecture (DIVA) system,” in Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European, 2002, pp. 767-770.
    [Bibtex]
    @INPROCEEDINGS{1471640,
    author={Herming Chiueh and Draper, J. and Mediratta, S. and Sondeen, J.},
    booktitle={Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European},
    title={The address translation unit of the data amp;#8211;intensive architecture (DIVA) system},
    year={2002},
    month={sept.},
    volume={},
    number={},
    pages={767 -770},
    keywords={},
    doi={},
    ISSN={},}
  • [DOI] J. Draper, J. Sondeen, S. Mediratta, and I. Kim, “Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip,” in Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on, 2002, pp. 163-172.
    [Bibtex]
    @INPROCEEDINGS{1030716,
    author={Draper, J. and Sondeen, J. and Mediratta, S. and Ihn Kim},
    booktitle={Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on},
    title={Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip},
    year={2002},
    month={july},
    volume={},
    number={},
    pages={ 163 - 172},
    keywords={0.18 micron;32 bit;DIVA;RISC processor;TSMC technology;bandwidth-limited applications;data-intensive architecture processing-in-memory chip;inherent memory bandwidth;microcontroller;multimedia applications;scalar processor;smart-memory coprocessors;sparse-matrix computations;coprocessors;microcontrollers;multimedia computing;reduced instruction set computing;sparse matrices;},
    doi={10.1109/ASAP.2002.1030716},
    ISSN={1063-6862 },}
  • [DOI] J. Draper, C. Jacqueline, M. Hall, C. Steele, T. Barrett, J. LaCoss, J. Granacki, J. Shin, C. Chen, C. W. Kang, I. Kim, and G. Daglikoca, “The architecture of the DIVA processing-in-memory chip,” in Proceedings of the 16th international conference on Supercomputing, New York, NY, USA, 2002, pp. 14-25.
    [Bibtex]
    @inproceedings{Draper:2002:ADP:514191.514197,
     author = {Draper, Jeff and Cha Jacqueline and Hall, Mary and Steele, Craig and Barrett, Tim and LaCoss, Jeff and Granacki, John and Shin, Jaewook and Chen, Chun and Kang, Chang Woo and Kim, Ihn and Daglikoca, Gokhan},
     title = {The architecture of the DIVA processing-in-memory chip},
     booktitle = {Proceedings of the 16th international conference on Supercomputing},
     series = {ICS '02},
     year = {2002},
     isbn = {1-58113-483-5},
     location = {New York, New York, USA},
     pages = {14--25},
     numpages = {12},
     url = {http://doi.acm.org/10.1145/514191.514197},
     doi = {http://doi.acm.org/10.1145/514191.514197},
     acmid = {514197},
     publisher = {ACM},
     address = {New York, NY, USA},
     keywords = {architecture, memory bandwidth, processing-in-memory},
    }
  • [DOI] J. Moon, W. C. Athas, P. A. Beerel, and J. T. Draper, “Low-power sequential access memory design,” in Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002, 2002, pp. 111-114.
    [Bibtex]
    @INPROCEEDINGS{1012778,
    author={Joong-Seok Moon and Athas, W.C. and Beerel, P.A. and Draper, J.T.},
    booktitle={Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002},
    title={Low-power sequential access memory design},
    year={2002},
    month={},
    volume={},
    number={},
    pages={111 -114},
    keywords={0.25 micron;1.2 V;344 muW;358 muW;40 MHz;CMOS process;high performance;locally-communicating sequencers;low-power memory design;sequential access memory;CMOS memory circuits;VLSI;integrated circuit design;low-power electronics;memory architecture;},
    doi={10.1109/CICC.2002.1012778},
    ISSN={},}

2001

  • [DOI] H. Chiueh, J. Draper, and J. Choma J., “A dynamic thermal management circuit for system-on-chip designs,” in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, p. 577 -580 vol.2.
    [Bibtex]
    @INPROCEEDINGS{957542,
    author={Chiueh, H. and Draper, J. and Choma, J., Jr.},
    booktitle={Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on},
    title={A dynamic thermal management circuit for system-on-chip designs},
    year={2001},
    month={},
    volume={2},
    number={},
    pages={577 -580 vol.2},
    keywords={0.25 micron;MOSIS;TSMC process;VLSI;continual monitoring;dynamic thermal management circuit;hardware requirements;multi-stage fan controller;on-chip power/speed modulation;power dissipation;system overhead;system-on-chip designs;thermal activity;MOS integrated circuits;VLSI;application specific integrated circuits;integrated circuit design;thermal management (packaging);},
    doi={10.1109/ICECS.2001.957542},
    ISSN={},}
  • [DOI] H. Chiueh, J. Draper, and J. Choma J., “A thermal management system and prototyping for system-on-chip designs,” in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 51-55.
    [Bibtex]
    @INPROCEEDINGS{914936,
    author={Herming Chiueh and Draper, J. and Choma, J., Jr.},
    booktitle={Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on},
    title={A thermal management system and prototyping for system-on-chip designs},
    year={2001},
    month={},
    volume={},
    number={},
    pages={51 -55},
    keywords={ circuit stability; feedback; high-speed circuit design; prototyping; system-on-chip designs; thermal management system; application specific integrated circuits; circuit stability; high-speed integrated circuits; integrated circuit design; integrated circuit packaging; thermal management (packaging);},
    doi={10.1109/SSMSD.2001.914936},
    ISSN={},}
  • [DOI] H. Chiueh, J. Draper, and J. C. Jr., “A programmable thermal management interface circuit for PowerPC systems,” Microelectronics Journal, vol. 32, iss. 10C11, pp. 875-881, 2001.
    [Bibtex]
    @article{Chiueh2001875,
    title = "A programmable thermal management interface circuit for PowerPC systems",
    journal = "Microelectronics Journal",
    volume = "32",
    number = "10C11",
    pages = "875 - 881",
    year = "2001",
    note = "",
    issn = "0026-2692",
    doi = "10.1016/S0026-2692(01)00076-3",
    url = "http://www.sciencedirect.com/science/article/pii/S0026269201000763",
    author = "Herming Chiueh and Jeffrey Draper and John Choma Jr.",
    keywords = "Thermal management",
    keywords = "Interface circuitry",
    keywords = "Temperature monitoring"
    }

2000

  • [DOI] L. Luh, J. Choma J., and J. Draper, “A high-speed fully differential current switch,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 47, iss. 4, pp. 358-363, 2000.
    [Bibtex]
    @ARTICLE{839672,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    journal={Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on},
    title={A high-speed fully differential current switch},
    year={2000},
    month={apr},
    volume={47},
    number={4},
    pages={358 -363},
    keywords={2 micron;50 MHz;CMOS process;SI sigma-delta modulator;capacitance matching;clock-feedthrough effect reduction;continuous-time SI Sigma; Delta; modulator;current-mode signal processing;dummy transistors;fully differential current switch;high-speed current switch;swing-reduced drivers;switched-current Sigma; Delta; modulator;switching transistors;CMOS analogue integrated circuits;analogue processing circuits;current-mode circuits;field effect transistor switches;high-speed integrated circuits;sigma-delta modulation;switched current circuits;switching circuits;},
    doi={10.1109/82.839672},
    ISSN={1057-7130},}
  • [DOI] L. Lah, J. Choma J., and J. Draper, “A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 47, iss. 4, pp. 363-369, 2000.
    [Bibtex]
    @ARTICLE{839673,
    author={Lah, L. and Choma, J., Jr. and Draper, J.},
    journal={Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on},
    title={A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications},
    year={2000},
    month={apr},
    volume={47},
    number={4},
    pages={363 -369},
    keywords={2 micron;270 muW;5 V;CMFB circuit;CMOS process;SI sigma-delta modulator;common-mode feedback circuit;compensation scheme;continuous-time circuit;high-impedance current-mode applications;input stage;long-channel differential-difference amplifier;stability;switched-current Sigma; Delta; modulator;two-stage high-gain architecture;wide input voltage range;CMOS analogue integrated circuits;circuit feedback;compensation;continuous time systems;current-mode circuits;electric impedance;sigma-delta modulation;switched current circuits;},
    doi={10.1109/82.839673},
    ISSN={1057-7130},}
  • L. Luh, J. Choma J., and J. Draper, “A 400MHz 5th-order CMOS continuous-time switched-current amp;#931; amp;#916; modulator,” in Solid-State Circuits Conference, 2000. ESSCIRC ’00. Proceedings of the 26rd European, 2000, pp. 33-36.
    [Bibtex]
    @INPROCEEDINGS{1471206,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European},
    title={A 400MHz 5th-order CMOS continuous-time switched-current amp;#931; amp;#916; modulator},
    year={2000},
    month={sept.},
    volume={},
    number={},
    pages={33 -36},
    keywords={},
    doi={},
    ISSN={},}
  • [DOI] H. Chiueh, J. Choma J., and J. Draper, “Implementation of a Temperature Monitoring Interface Circuit for PowerPC systems,” in Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, 2000, p. 98 -101 vol.1.
    [Bibtex]
    @INPROCEEDINGS{951595,
    author={Chiueh, H. and Choma, J., Jr. and Draper, J.},
    booktitle={Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on},
    title={Implementation of a Temperature Monitoring Interface Circuit for PowerPC systems},
    year={2000},
    month={},
    volume={1},
    number={},
    pages={98 -101 vol.1},
    keywords={0.5 micron;50 MHz;HP single-poly three-metal MOSIS process;ITEM multi-node computer system;Lager;PowerPC system;Powerview;integrated thermal management system;temperature monitoring interface circuit;microcomputers;monitoring;temperature sensors;thermal management (packaging);},
    doi={10.1109/MWSCAS.2000.951595},
    ISSN={},}
  • [DOI] C. W. Kang and J. Draper, “A fast, simple router for the Data-Intensive Architecture (DIVA) system,” in Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, 2000, p. 188 -192 vol.1.
    [Bibtex]
    @INPROCEEDINGS{951617,
    author={Chang Woo Kang and Draper, J.},
    booktitle={Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on},
    title={A fast, simple router for the Data-Intensive Architecture (DIVA) system},
    year={2000},
    month={},
    volume={1},
    number={},
    pages={188 -192 vol.1},
    keywords={0.5 micron;3.3 V;5.12 Gbit/s;80 MHz;CMOS signaling;DIVA system;Red Rover algorithm;bidirectional ring;channel bandwidth;data-intensive architecture;embedded DRAM technology;latency;router design;short-cut FIFO data path;throughput;CMOS digital integrated circuits;DRAM chips;embedded systems;network routing;},
    doi={10.1109/MWSCAS.2000.951617},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., and J. Draper, “Performance optimization for high-order continuous-time Sigma; Delta; modulators with extra loop delay,” in Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, 2000, p. 669 -672 vol.5.
    [Bibtex]
    @INPROCEEDINGS{857563,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on},
    title={Performance optimization for high-order continuous-time Sigma; Delta; modulators with extra loop delay},
    year={2000},
    month={},
    volume={5},
    number={},
    pages={669 -672 vol.5},
    keywords={circuit architecture;high-order continuous-time sigma-delta modulators;loop delay;sampling rate;single-loop architecture;stability;circuit optimisation;circuit stability;continuous time systems;delays;sigma-delta modulation;},
    doi={10.1109/ISCAS.2000.857563},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., and J. Draper, “A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes,” in Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, 2000, p. 65 -68 vol.5.
    [Bibtex]
    @INPROCEEDINGS{857364,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on},
    title={A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes},
    year={2000},
    month={},
    volume={5},
    number={},
    pages={65 -68 vol.5},
    keywords={0.5 micron;ESD clamping;ESD protection circuit;I/O pads;Zener-diode-activated ESD protection;electrostatic discharge protection;high-speed ESD test;human body model;latchup-free characteristic;overshoot attenuation;poly-antenna effect protection;silicide block capability;submicron CMOS processes;substrate p-n-p transistor;CMOS integrated circuits;Zener diodes;electrostatic discharge;protection;},
    doi={10.1109/ISCAS.2000.857364},
    ISSN={},}
  • [DOI] H. Chiueh, L. Luh, J. Draper, and J. Choma J., “A novel fully integrated fan controller for advanced computer systems,” in Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on, 2000, pp. 191-194.
    [Bibtex]
    @INPROCEEDINGS{836472,
    author={Chiueh, H. and Luh, L. and Draper, J. and Choma, J., Jr.},
    booktitle={Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on},
    title={A novel fully integrated fan controller for advanced computer systems},
    year={2000},
    month={},
    volume={},
    number={},
    pages={191 -194},
    keywords={PWM drive;advanced computer systems;cost;embedded multicomputer system;fully integrated fan controller;integrated hierarchical thermal management scheme;linear drive;pure digital design;cooling;digital control;embedded systems;multiprocessing systems;pulse width modulation;thermal management (packaging);},
    doi={10.1109/SSMSD.2000.836472},
    ISSN={},}

1999

  • [DOI] M. Hall, P. Kogge, J. Koller, P. Diniz, C. Jacqueline, J. Draper, J. LaCoss, J. Granacki, J. Brockman, A. Srivastava, W. Athas, V. Freeh, J. Shin, and J. Park, “Mapping irregular applications to DIVA, a PIM-based data-intensive architecture,” in Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM), New York, NY, USA, 1999.
    [Bibtex]
    @inproceedings{Hall:1999:MIA:331532.331589,
     author = {Hall, Mary and Kogge, Peter and Koller, Jeff and Diniz, Pedro and Cha Jacqueline and Draper, Jeff and LaCoss, Jeff and Granacki, John and Brockman, Jay and Srivastava, Apoorv and Athas, William and Freeh, Vincent and Shin, Jaewook and Park, Joonseok},
     title = {Mapping irregular applications to DIVA, a PIM-based data-intensive architecture},
     booktitle = {Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM)},
     series = {Supercomputing '99},
     year = {1999},
     isbn = {1-58113-091-0},
     location = {Portland, Oregon, United States},
     articleno = {57},
     url = {http://doi.acm.org/10.1145/331532.331589},
     doi = {http://doi.acm.org/10.1145/331532.331589},
     acmid = {331589},
     publisher = {ACM},
     address = {New York, NY, USA},
    }
  • L. Luh, J. Choma J., J. Draper, and H. Chiueh, “A high amp;#8211;speed CMOS on amp;#8211;chip temperature sensor,” in Solid-State Circuits Conference, 1999. ESSCIRC ’99. Proceedings of the 25th European, 1999, pp. 290-293.
    [Bibtex]
    @INPROCEEDINGS{1471153,
    author={Luh, L. and Choma, J., Jr. and Draper, J. and Chiueh, H.},
    booktitle={Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European},
    title={A high amp;#8211;speed CMOS on amp;#8211;chip temperature sensor},
    year={1999},
    month={sept.},
    volume={},
    number={},
    pages={290 -293},
    keywords={},
    doi={},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., J. Draper, and H. Chiueh, “A high-speed digital comb filter for Sigma; Delta; analog-to-digital conversion,” in Circuits and Systems, 1999. 42nd Midwest Symposium on, 1999, p. 356 -359 vol. 1.
    [Bibtex]
    @INPROCEEDINGS{867279,
    author={Luh, L. and Choma, J., Jr. and Draper, J. and Herming Chiueh},
    booktitle={Circuits and Systems, 1999. 42nd Midwest Symposium on},
    title={A high-speed digital comb filter for Sigma; Delta; analog-to-digital conversion},
    year={1999},
    month={},
    volume={1},
    number={},
    pages={356 -359 vol. 1},
    keywords={1.2 micron;115 MHz;35 mW;5 V;active area;carry-saved adders;circuit design;digital decimator;high-speed digital comb filter;length;order;power consumption;sigma-delta analog-to-digital conversion;systematic modular design;adders;comb filters;digital filters;high-speed integrated circuits;sigma-delta modulation;},
    doi={10.1109/MWSCAS.1999.867279},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., and J. Draper, “Circuit design challenges for high-speed CMOS continuous-time switched-current Sigma; Delta; modulators,” in Circuits and Systems, 1999. 42nd Midwest Symposium on, 1999, p. 43 -46 vol. 1.
    [Bibtex]
    @INPROCEEDINGS{867204,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Circuits and Systems, 1999. 42nd Midwest Symposium on},
    title={Circuit design challenges for high-speed CMOS continuous-time switched-current Sigma; Delta; modulators},
    year={1999},
    month={},
    volume={1},
    number={},
    pages={43 -46 vol. 1},
    keywords={cascade structure;circuit design;high-order single loop structure;high-performance architecture;high-speed operation;integrator capacitor mismatching;loop delay;low-pass CMOS continuous-time switched-current Sigma; Delta; modulator;multi-bit quantizer;parallelism;transfer function;wide-bandwidth conversion;CMOS integrated circuits;continuous time systems;high-speed integrated circuits;sigma-delta modulation;switched current circuits;transfer functions;},
    doi={10.1109/MWSCAS.1999.867204},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., and J. Draper, “A self-sensing tristate pad driver for control signals of multiple bus controllers,” in Circuits and Systems, 1999. ISCAS ’99. Proceedings of the 1999 IEEE International Symposium on, 1999, p. 447 -450 vol.1.
    [Bibtex]
    @INPROCEEDINGS{777909,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on},
    title={A self-sensing tristate pad driver for control signals of multiple bus controllers},
    year={1999},
    month={jul},
    volume={1},
    number={},
    pages={447 -450 vol.1},
    keywords={address map;bus controllers;capacitive loads;handshaking signals;high-speed operation;internal control signal;multiple bus controllers;self-sensing tristate pad driver;single-board computers;circuit feedback;driver circuits;high-speed integrated circuits;microcomputers;system buses;},
    doi={10.1109/ISCAS.1999.777909},
    ISSN={},}
  • [DOI] L. Luh, J. Chroma J., and J. Draper, “Area-efficient area pad design for high pin-count chips,” in VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on, 1999, pp. 78-81.
    [Bibtex]
    @INPROCEEDINGS{757381,
    author={Luh, L. and Chroma, J., Jr. and Draper, J.},
    booktitle={VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on},
    title={Area-efficient area pad design for high pin-count chips},
    year={1999},
    month={mar},
    volume={},
    number={},
    pages={78 -81},
    keywords={0.8 micron;area pad design;area pad layout method;area-efficient pad design;diffusion contact spacing requirement;driver size reduction;embedded multicomputer router interface chip;high pin-count chips;interconnection pads;pad drivers;serpentine gate layout;silicided diffusion;single-poly 3-metal N-well CMOS process;top metal layer;well contact;CMOS integrated circuits;VLSI;integrated circuit layout;},
    doi={10.1109/GLSV.1999.757381},
    ISSN={},}

1998

  • [DOI] H. Chiueh, J. Draper, L. Luh, and J. Choma J., “A novel model for on-chip heat dissipation,” in Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on, 1998, pp. 779-782.
    [Bibtex]
    @INPROCEEDINGS{743937,
    author={Chiueh, H. and Draper, J. and Luh, L. and Choma, J., Jr.},
    booktitle={Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on},
    title={A novel model for on-chip heat dissipation},
    year={1998},
    month={nov},
    volume={},
    number={},
    pages={779 -782},
    keywords={IC packages;VLSI design;analytical model;circuit location;circuit reliability analysis;default offset temperature;electrothermal analysis;heat transport properties;junction temperature prediction;mixed-signal VLSI;on-chip heat dissipation;test configuration;VLSI;cooling;integrated circuit design;integrated circuit modelling;integrated circuit packaging;temperature distribution;thermal analysis;},
    doi={10.1109/APCCAS.1998.743937},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., and J. Draper, “A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application,” in Electronics, Circuits and Systems, 1998 IEEE International Conference on, 1998, p. 347 -350 vol.3.
    [Bibtex]
    @INPROCEEDINGS{814006,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Electronics, Circuits and Systems, 1998 IEEE International Conference on},
    title={A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application},
    year={1998},
    month={},
    volume={3},
    number={},
    pages={347 -350 vol.3},
    keywords={1 MHz;2 micron;50 MHz;CMOS process;common-mode feedback circuit;common-mode voltage offset;compensation scheme;continuous-time Sigma; Delta; modulator;continuous-time circuit;high-impedance current mode application;sigma-delta modulator;stability;switched-current Sigma; Delta; modulator;two-stage high-gain architecture;CMOS analogue integrated circuits;analogue processing circuits;circuit feedback;circuit stability;continuous time systems;current-mode circuits;modulators;sigma-delta modulation;switched current circuits;},
    doi={10.1109/ICECS.1998.814006},
    ISSN={},}
  • [DOI] L. Luh, J. Choma J., and J. Draper, “A high-speed fully differential current switch,” in Electronics, Circuits and Systems, 1998 IEEE International Conference on, 1998, p. 343 -346 vol.3.
    [Bibtex]
    @INPROCEEDINGS{814005,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Electronics, Circuits and Systems, 1998 IEEE International Conference on},
    title={A high-speed fully differential current switch},
    year={1998},
    month={},
    volume={3},
    number={},
    pages={343 -346 vol.3},
    keywords={1 MHz;1.75 to 5 V;2 micron;20 to 100 MHz;50 MHz;CMOS process;clock-feedthrough effect;continuous-time Sigma; Delta; modulator;current spikes reduction;dummy transistors;fully differential current switch;high-speed current switch;high-speed current-mode signal processing;sigma-delta modulator;swing-reduced drivers;switched-current Sigma; Delta; modulator;switching speed;switching transistors;CMOS analogue integrated circuits;analogue processing circuits;current-mode circuits;driver circuits;field effect transistor switches;modulators;sigma-delta modulation;signal processing;switched current circuits;},
    doi={10.1109/ICECS.1998.814005},
    ISSN={},}
  • H. Chiueh, J. Draper, L. Luh, and J. Choma, “A thermal evaluation of integrated circuits: On chip offset temperature measurement and modeling,” in Proc. 2nd Internationl Workshop on Design of Mixed-Mode Integrated Circuits and Applications, 1998, pp. 109-113.
    [Bibtex]
    @INPROCEEDINGS{Chiueh98jr,
        author = {Herming Chiueh and Jeffrey Draper and Louis Luh and John Choma},
        title = {A thermal evaluation of integrated circuits: On chip offset temperature measurement and modeling},
        booktitle = {Proc. 2nd Internationl Workshop on Design of Mixed-Mode Integrated Circuits and Applications},
        year = {1998},
        pages = {109 -113}
    }
  • [DOI] L. Luh, J. Choma J., and J. Draper, “A 50-MHz continuous-time switched-current Sigma; Delta; modulator ,” in Circuits and Systems, 1998. ISCAS ’98. Proceedings of the 1998 IEEE International Symposium on, 1998, p. 579 -582 vol.1.
    [Bibtex]
    @INPROCEEDINGS{704578,
    author={Luh, L. and Choma, J., Jr. and Draper, J.},
    booktitle={Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on},
    title={A 50-MHz continuous-time switched-current Sigma; Delta; modulator },
    year={1998},
    month={may-3 jun},
    volume={1},
    number={},
    pages={579 -582 vol.1},
    keywords={1 MHz;15 mW;2 micron;5 V;50 MHz;8 bit;CMOS process;clock feedthrough problem;continuous-time SI Sigma; Delta; modulator;current switch;reference current generator;second-order type;sigma-delta modulator;switched-current Sigma; Delta; modulator;CMOS integrated circuits;circuit stability;continuous time systems;mixed analogue-digital integrated circuits;modulators;sigma-delta modulation;switched current circuits;},
    doi={10.1109/ISCAS.1998.704578},
    ISSN={},}
  • C. Steele, J. Draper, and J. Koller, “Safety Net: Secure Communications for Embedded High-Performance Computing,” in Lecture Notes in Computer Science 1388 (IPPS/SPDP’98 Workshops Proceedings), 1998.
    [Bibtex]
    @INPROCEEDINGS{Steele:1998:SNS,
      author =       {C. Steele and J. Draper and J. Koller},
      title =        {Safety Net: Secure Communications for Embedded High-Performance Computing},
      booktitle =     {Lecture Notes in Computer Science 1388 (IPPS/SPDP'98 Workshops Proceedings)},
      volume =       {1388},
      year =         {1998},
      ISSN =         {0302-9743}, }
  • J. Draper, J. Block, J. Koller, and C. Steele, “Thermal Management in Embedded Systems Using MEMS,” in Lecture Notes in Computer Science 1388 (IPPS/SPDP’98 Workshops Proceedings), 1998.
    [Bibtex]
    @INPROCEEDINGS{Steele:1998:SNS,
      author =       {J. Draper and Jay Block and J. Koller and C. Steele},
      title =        {Thermal Management in Embedded Systems Using MEMS},
      booktitle =     {Lecture Notes in Computer Science 1388 (IPPS/SPDP'98 Workshops Proceedings)},
      volume =       {1388},
      year =         {1998},
      ISSN =         {0302-9743}, }
  • [DOI] L. Luh, J. Choma, and J. Draper, “A continuous-time switched-current Sigma; Delta; modulator with reduced loop delay,” in VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on, 1998, pp. 286-291.
    [Bibtex]
    @INPROCEEDINGS{665270,
    author={Luh, L. and Choma, J. and Draper, J.},
    booktitle={VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on},
    title={A continuous-time switched-current Sigma; Delta; modulator with reduced loop delay},
    year={1998},
    month={feb},
    volume={},
    number={},
    pages={286 -291},
    keywords={16.6 mW;2 micron;5 V;50 MHz;active area;continuous-time switched-current Sigma; Delta; modulator;dynamic range;high-speed current-mode comparator;integrator gain;loop delay;power dissipation;predicted states;scaled current mode signals;summing;comparators (circuits);delays;integrating circuits;sigma-delta modulation;switched current circuits;},
    doi={10.1109/GLSV.1998.665270},
    ISSN={1066-1395},}

1997

  • [DOI] C. S. Steele, J. Draper, J. Koller, and C. LaCour, “A bus-efficient low-latency network interface for the PDSS multicomputer,” in High Performance Distributed Computing, 1997. Proceedings. The Sixth IEEE International Symposium on, 1997, pp. 213-222.
    [Bibtex]
    @INPROCEEDINGS{626407,
    author={Steele, C.S. and Draper, J. and Koller, J. and LaCour, C.},
    booktitle={High Performance Distributed Computing, 1997. Proceedings. The Sixth IEEE International Symposium on},
    title={A bus-efficient low-latency network interface for the PDSS multicomputer},
    year={1997},
    month={aug},
    volume={},
    number={},
    pages={213 -222},
    keywords={PDSS multicomputer;bus-efficient low-latency network interface;cache coherence protocols;cache-to-cache communications;commodity processor;distributed barrier-synchronization mechanism;interconnect;routing;single-chip implementation;unprivileged code;memory protocols;multiprocessor interconnection networks;network interfaces;performance evaluation;telecommunication network routing;},
    doi={10.1109/HPDC.1997.626407},
    ISSN={},}
  • J. T. Draper and F. Petrini, “Routing in Bidirectional k-ary n-cubes with the Red Rover Algorithm,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1997, June 30 – July 3, 1997, Las Vegas, Nevada, USA, 1997, pp. 1184-1193.
    [Bibtex]
    @inproceedings{DraperP97,
      title = {Routing in Bidirectional k-ary n-cubes with the Red Rover Algorithm},
      author = {Jeffrey T. Draper and Fabrizio Petrini},
      year = {1997},
      pages = {1184-1193},
      booktitle = {Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1997, June 30 - July 3, 1997, Las Vegas, Nevada, USA},
      publisher = {CSREA Press},
      isbn = {0-9648666-8-4},
    }
  • J. Koller, J. Block, J. Draper, C. Lacour, and C. Steele, “Lessons from Three Generations of Embeddable Supercomputers,” in The Second International Workshop on Embedded HPC Systems and Applications, Geneva, Switzerland, 1997.
    [Bibtex]
    @inproceedings{Lessons ,
      title = {Lessons from Three Generations of Embeddable Supercomputers},
      author = {J. Koller and J. Block and J. Draper and C. Lacour and C. Steele},
      year = {1997},
      booktitle = {The Second International Workshop on Embedded HPC Systems and Applications, Geneva, Switzerland},
    }

1996

  • J. T. Draper, “The Red Rover Algorithm for Deadlock-Free Routing on Bidirectional Rings,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1996, August 9-11, 1996, Sunnyvale, California, USA, 1996, pp. 345-354.
    [Bibtex]
    @inproceedings{Draper96,
      title = {The Red Rover Algorithm for Deadlock-Free Routing on Bidirectional Rings},
      author = {Jeffrey T. Draper},
      year = {1996},
      tags = {routing},
      pages = {345-354},
      booktitle = {Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1996, August 9-11, 1996, Sunnyvale, California, USA},
      publisher = {CSREA Press},
      isbn = {0-9648666-4-1},
    }

1994

  • [DOI] J. T. Draper and J. Ghosh, “A comprehensive analytical model for wormhole routing in multicomputer systems,” J. Parallel Distrib. Comput., vol. 23, pp. 202-214, 1994.
    [Bibtex]
    @article{Draper:1994:CAM:196141.196156,
     author = {Draper, Jeffrey T. and Ghosh, Joydeep},
     title = {A comprehensive analytical model for wormhole routing in multicomputer systems},
     journal = {J. Parallel Distrib. Comput.},
     volume = {23},
     issue = {2},
     month = {November},
     year = {1994},
     issn = {0743-7315},
     pages = {202--214},
     numpages = {13},
     url = {http://dl.acm.org/citation.cfm?id=196141.196156},
     doi = {10.1006/jpdc.1994.1132},
     acmid = {196156},
     publisher = {Academic Press, Inc.},
     address = {Orlando, FL, USA},
    }
  • [DOI] J. T. Draper and J. Ghosh, “The M-cache: A message-handling mechanism for multicomputer systems,” Parallel Computing, vol. 20, iss. 9, pp. 1269-1288, 1994.
    [Bibtex]
    @article{Draper19941269,
    title = "The M-cache: A message-handling mechanism for multicomputer systems",
    journal = "Parallel Computing",
    volume = "20",
    number = "9",
    pages = "1269 - 1288",
    year = "1994",
    note = "",
    issn = "0167-8191",
    doi = "10.1016/0167-8191(94)90037-X",
    url = "http://www.sciencedirect.com/science/article/pii/016781919490037X",
    author = "Jeffrey T. Draper and Joydeep Ghosh",
    keywords = "Multicomputer systems",
    keywords = "M-cache",
    keywords = "Programming environments",
    keywords = "Message-directed programming",
    keywords = "Performance evaluation"
    }

1993

  • [DOI] J. Ghosh, K. D. Goveas, and J. T. Draper, “Performance evaluation of a parallel I/O subsystem for hypercube multicomputers,” J. Parallel Distrib. Comput., vol. 17, pp. 90-106, 1993.
    [Bibtex]
    @article{Ghosh:1993:PEP:163506.163516,
     author = {Ghosh, Joydeep and Goveas, Kelvin D. and Draper, Jeffrey T.},
     title = {Performance evaluation of a parallel I/O subsystem for hypercube multicomputers},
     journal = {J. Parallel Distrib. Comput.},
     volume = {17},
     issue = {1-2},
     month = {January},
     year = {1993},
     issn = {0743-7315},
     pages = {90--106},
     numpages = {17},
     url = {http://dl.acm.org/citation.cfm?id=163506.163516},
     doi = {10.1006/jpdc.1993.1007},
     acmid = {163516},
     publisher = {Academic Press, Inc.},
     address = {Orlando, FL, USA},
    }

1992

  • [DOI] J. T. Draper and J. Ghosh, “Multipath E-Cube Algorithms (MECA) for Adaptive Wormhole Routing and Broadcasting in itk-ary itn-Cubes,” in Proceedings of the 6th International Parallel Processing Symposium, Washington, DC, USA, 1992, pp. 407-410.
    [Bibtex]
    @inproceedings{Draper:1992:MEA:645603.662271,
     author = {Draper, Jeffrey T. and Ghosh, Joydeep},
     title = {Multipath E-Cube Algorithms (MECA) for Adaptive Wormhole Routing and Broadcasting in itk-ary itn-Cubes},
     booktitle = {Proceedings of the 6th International Parallel Processing Symposium},
     series = {IPPS '92},
     year = {1992},
     isbn = {0-8186-2672-0},
     pages = {407--410},
     numpages = {4},
     url = {http://dx.doi.org/10.1109/IPPS.1992.223011},
     doi = {http://dx.doi.org/10.1109/IPPS.1992.223011},
     acmid = {662271},
     publisher = {IEEE Computer Society},
     address = {Washington, DC, USA},
     keywords = {wormhole broadcasting, source node, adaptive wormhole routing, multipath E-cube algorithm, fault-tolerant wormhole routing, multiple shortest paths, destination node, multicomputer, virtual channels, physical channel, network throughput, circuit-switched routing, multiple broadcast trees},
    }

1991

  • [DOI] J. T. Draper, J. Ghosh, and W. C. Athas, “The M-cache: a message-retrieving mechanism for multicomputer systems,” in Parallel and Distributed Processing, 1991. Proceedings of the Third IEEE Symposium on, 1991, pp. 258-265.
    [Bibtex]
    @INPROCEEDINGS{218271,
    author={Draper, J.T. and Ghosh, J. and Athas, W.C.},
    booktitle={Parallel and Distributed Processing, 1991. Proceedings of the Third IEEE Symposium on},
    title={The M-cache: a message-retrieving mechanism for multicomputer systems},
    year={1991},
    month={dec},
    volume={},
    number={},
    pages={258 -265},
    keywords={M-cache;concurrent algorithms;intelligent memory;message search;message-retrieving mechanism;multicomputer systems;speedup measures;buffer storage;parallel algorithms;parallel architectures;},
    doi={10.1109/SPDP.1991.218271},
    ISSN={},}