Microarchitecture and Integrated Circuits Research Group


Integrity and Reliability in Integrated Circuits, DARPA, February 2011 – present

The DARPA Integrity and Reliability in IC program is fostering the development of technology for deriving the functionality of an IC to determine unambiguously if undocumented functionality has been incorporated somewhere along the fabrication chain, and to accurately determine the IC’s useful lifespan from a physical perspective. Since ICs are at the core of most systems and provide the critical functionalities that differentiate systems (e.g., detection and signal processing, targeting, and processing), changes such as additions in functionality or intentionally reduced lifespan could cause faulty operation. Our primary task on the program will develop a series of designs/chips that will be used to test the integrity and reliability assessment technology under development by the IRIS program. System-on-chip and multi-core architecture research will be leveraged in the test chip design.


Object-Accelerated Computational Fabric, DARPA / Exogi, LLC, November 2010 – present

RISC instruction sets exist because they are easy to decode and pipeline, but they have relatively low information density and operate on similarly primitive data types. However, the codes these CPUs are typically running today are largely object-oriented languages, with either static or dynamic method dispatch. Programmer productivity is a relatively constant number of lines of code per day, whether assembly language or a much higher-level abstraction such as a modern object-based language. The information density and expressivity of an object-oriented language are much greater, and the computational effort induced by each object method invocation can be much greater, than those of conventional languages for which our RISC processors were developed. In response, the OACF project seeks to:

  •  Raise the level of abstraction in RISC-based hardware by supporting an efficient set of object-oriented hardware features.
  • Recognize that data transfer, prefetching, sharing and caching can be vastly more efficient if structural information that is currently discarded when compiling object-oriented programs to RISC instructions can be exploited by low-level hardware elements.
  • Realize that the ultimate scalability of systems on a chip (SoC) designs requires a revolutionary reduction in network interface overhead, and
  • Revamp the processing model to make the central processing unit a coordinator of networked heterogeneous specialist co-processors rather than the primary locus of computation for a whole system.


Radiation Effects on Electronics in Aligned Carbon Nanotube Technology, DTRA, June  2010 – present

CMOS scaling below the 100 nm feature size is increasingly challenging the reliable operation of commercial-process-based electronics in space and strategic radiation environments. Concurrently emerging are carbon-nanotube-based technologies that already exhibit performances rivaling the most advanced CMOS processes while showing a promising inherent resilience to radiation. In consideration of these developments, the RadCNT project is exploring the basic mechanisms and phenomena from ionizing and non-ionizing radiation effects on field-effect transistors and circuits, based on self- aligned carbon nanotube technology. The multi-year effort’s objective is to gradually combine TCAD molecular modeling and simulation of CNTs with basic device fabrication and experimental radiation testing, for the purpose of establishing a fundamental understanding of underlying radiation mechanisms and their effects, from basic FET structures to logic gates and ultimately simple integrated circuits.


Resilient Computing, SRC/DARPA, November 2009 – present

Exploration of resilient computing techniques is being conducted as part of the Multi-Scale Systems Center (MuSyc), sponsored by MARCO and DARPA under the Focus Center Research Program. MARCO is a wholly-owned subsidiary of the Semiconductor Research Corporation. MuSyc is directed by Jan Rabaey of the University of California at Berkeley. The research is specifically addressing the areas of energy versus resilience trade-offs in fault-tolerant networks-on-chip and memories.


Trusted in Integrated Circuits, DARPA, October 2007 – present

The DARPA Trust in IC program has observed the trend of foundries and design houses moving off-shore. The program is attempting to develop techniques for guaranteeing that the devices that come back from fabrication identically match the designs submitted, specifically that no “Trojan horses” have been inserted to the design.  While obvious national security issues are involved in such a paradigm, in an academic sense, the program involves techniques for demonstrating proofs of correctness.  Our primary role on the program is to provide ASIC test chips that can serve as testbeds for demonstrating such techniques.  The program is a phased program starting with smaller ASICs and building up to 100M-transistor chips by the final phase.  Multi-core and network-on-chip architecture research has been included in the final phases.